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Memory is an important part of virtually every electronic system, yet it's increasingly becoming a performance bottleneck. The latest ONFi 3.0 (Open NAND Flash Interface) specification promises to ease this bottleneck for nonvolatile memory. But silicon IP support is needed to facilitate adoption, and Cadence is stepping forward today (Jan. 9, 2012) with the first integrated ONFi 3.0 controller and PHY IP solution. Here's some background on ONFi 3.0 and its importance to system-on-chip (SoC) designers.
While NAND flash is increasingly important in consumer and computing applications, before 2006 there was no standard to help designers integrate NAND flash components with SoC designs. Bob Pierce, senior technical marketing manager at Cadence, noted that SoC designers used asynchronous interfaces with proprietary timing. In 2006 the ONFi working group formed and developed ONFi 1.0, which was basically an asynchronous interface with standardized timing.
In 2008 the working group published ONFi 2.0, which is a dual data rate (DDR) synchronous interface. It delivers speeds up to 200 MT/second. The ONFi 2.1 specification, which followed in 2009, added some new features, and later that year came ONFi 2.2, which allowed more efficient operation with logic unit number (LUN) reset and enhanced page register clear. This is the version most manufacturers are shipping today. You can read a detailed specification history and download the specifications from the ONFi web site.
The big difference with ONFi 3.0, published March 2011, is performance - it pushes data transfer rates to 400 MT/second, doubling that of ONFi 2.2. This speed is made possible by a bidirectional source-synchronous DQS and scalable I/O interface. In addition to getting better performance, designers can reduce the number of channels.
The following chart provides other comparisons between ONFi 3.0 and ONFi 2.2. In ONFi 3.0, the 1.8 I/O voltage and the on-die termination both help reduce power. Volume addressing is a virtual addressing scheme that can reduce the number of chip enable pins. A recent ONFi 2.3 spec also includes this scheme.
ONFi 3.0 provides backwards compatibility to previous specifications, and does not require any re-qualification of drivers. As Pierce noted, ONFi 3.0 will be especially attractive for designs that use multiple channels.
Denali Software, acquired by Cadence in 2010, was the first IP provider to support ONFi 1.0. Now, Pierce observed, Cadence is the first provider to offer an integrated solution with the controller IP, PHY IP, firmware, memory models, and verification IP. An integrated controller and PHY solution are important because the interaction between the two is extremely complex, he noted. The Cadence NAND solution for ONFi 3.0 is shown below.
The Cadence ONFi 3.0 solution includes chip-enable interleaving, configurable error correction, hardware acceleration of key features, and LUN and chip enable operation. It also supports Toggle 2.0, an alternative specification that provides a "non-clocked" DDR capability by doing transfers on strobes. Additionally, the Cadence solution supports ONFi 2.3 and is backward-compatible with all previous ONFi and Toggle specifications.
Significantly, the announcement is taking place this week at the Storage Visions conference in Las Vegas, where Cadence, for the first time, is a conference sponsor. It's more evidence of the increasing emphasis that Cadence is placing on memory IP.
For further insights into ONFi 3.0, see Steve Leibson's Denali Memory Report blog.
Onwards ONFI#2.1 , there is support for Multi-plane (Interleaved ) concurrent and overlapped operation.
I would like to know ,How many register (ADD,CMD,STATUS) required for following operation
1. Multi-plane Overlapped 2. Multi-plane Concurrent
for per LUN.