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If you're an IC packaging or PCB designer, there's a free one-day event just for you at the Cadence San Jose, California headquarters March 15, 2012. Coming one day after CDNLive! Silicon Valley, the event will feature product/technology roadmaps, an interactive roundtable discussion, and half-day "techtorials" on design planning and signal integrity.
The event will start with registration at 8:00 a.m. and a welcoming address at 8:45 a.m. The morning session will include roadmaps for design authoring, PCB layout and routing, signal integrity, and chip packaging. It will conclude with a roundtable discussion with senior engineering directors and architects for PCB and IC packaging products.
The afternoon session will be comprised of the two four-hour techtorials. In the design planning techtorial, Robert Jordan, senior design engineer at FreedomCAD, will share his experiences using the Allegro PCB Designer Flow Planner. This product makes it possible to capture routing intent, and it provides feedback from the routing engine, shortening design times and reducing the number of layers. Users can create abstracted interconnect data, and the tool provides a visual/spatial map (below) of the open area in relation to the data and the user's design intent.
In the other techtorial, Terry Jemberg, principal product engineer at Cadence, will teach the basics of transmission line theory, terminations, crosstalk, and PCB stack-up design. The presentation will show how PCB designers can make decisions during the layout process.
Registration is required for this event. To register, click here. For further information, click here.
CDNLive! PCB Track
Meanwhile, the second day of CDNLive! Silicon Valley - March 14, 2012 - features a full day of user co-authored papers for PCB and IC package design. These sessions will be offered at the Doubletree Hotel in San Jose, California. Here's what you can expect.
9:00am:A Comprehensive Analysis and Verification Methodology for DDR3 InterfacesJerry Long, EMA, discusses how Allegro PCB SI and TimingDesigner® work together to achieve timing closure on DDR3 memory subsystems
10:00am:Accelerating the Methodology of PCB PDN Design and AnalysisDennis Nagle, Cadence, will update you on the latest PDN analysis technology introduced in 16.5
11:00am:PCB and Package Co-Design Using 3D EM full-wave simulationAntonio Ciccomancini, CST, updates you on Microwave Studio integration with Cadence PCB and IC packaging products
1:30pm:Why Doesn't My Board Work?James Hixson, ADIVA, presents a methodology to discover hidden design flaws to ensure the board you send to your fabricator will work the first time
2:30pm:The 21st Century Approach to Transferring Design Data to ManufacturingGary Carter, Fujitsu Networks Communications, will update you on IPC-2581 to streamline design data transfer to manufacturing
2:30pm:Multi-Chip Module (MCM) Package Design Flow Using Cadence SiP Design Tools and Agilent Package AnalysisSufia Salim, Analog Devices, discusses how Cadence SiP tools integrated with Cadence Virtuoso and ADS were used for cell phone towers and base station products
3:45pm:Creating Apps for OrCAD Capture: Experiences, Tips, and ExamplesNikhil Punnakkali, EMA Design Automation, discusses lessons learned on creating apps (for Capture and PCB Editor) for the OrCAD Capture Marketplace
3:45pm:Using Co-Design to Optimize System Interconnect PathsBroadcom and Cadence co-present how Broadcom used a single canvas co-design methodology to shorten their design cycle
4:45pm:Improving IDF Geometry DefinitionsRon Dallas, Teradyne, discusses the creation of a new sub-class for IDF geometry for your PCB library
4:45pm:Silicon-Package-Board Co-Design and Co-Analysis for a High-Performance Multi-Core ChipTilera, Bayside Design, and Cadence co-present a new methodology to optimize and analyze chip-package-board using a single canvas
Registration for CDNLive! is required. For further information, click here.