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If you're designing or planning to design at
20nm - or you're just curious about this emerging and much-discussed process
node - three free webinars May 1, 2 and 3 will provide a wealth of
valuable information. In these webinars, Cadence experts will team up with
industry leaders to present 20nm challenges and solutions, and provide guidance
that will help assure 20nm success.
You are welcome to attend one or all three of
1, 9:00 am Pacific: Cadence, TSMC and Others Outline their Vision for 20nm
Silicon Success (hosted by EE Times). Find out what it takes
to enable foundry-optimized, higher-performance, lower-power designs at 20nm.
Register to attend
May 2, 9:00 am Pacific: Cadence and Samsung Present a Digital
This webinar will dig deep into the requirements for, and the technology
behind, the ultimate in 20nm digital design and signoff. Get the inside scoop
from Cadence and Samsung on their experiences, best practices, and recommendations
Register to attend
May 3, 9:00 am Pacific: Cadence Presents a Custom 20nm Solution
Analog and full custom design at 20nm will present a significant challenge for
design engineers and layout designers. Hear about addressing the challenges of
20nm design with double patterning-aware analog and custom blocks and IP. See a
demonstration of dynamic coloring and hear about a 20nm design example from
concept to tapeout.
Register to attend
In addition to what you'll learn, attendees will
be entered into a drawing to win an Apple iPad. Click here
for more information about the webinars.
20nm Industry Insights blog posts:
Q&A: A Look at 20nm Design Challenges and
ISQED Keynote: 20nm From a Custom/Analog
GTC Presentation: Cadence Outlines Comprehensive
20nm Design Flow
On-Line Presentation: 20nm Design Challenges, and
a Look Ahead to 14nm