Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
While many low-power design techniques are available to IC designers, the greatest potential for power savings is at the system level, where both software and hardware can be considered. So what's standing in the way of system-level low power design, and what needs to happen to make it practical? Qi Wang, group director for solutions marketing at Cadence, provided some answers in a recent talk at the Electronic Design Processes Symposium (EDPS 2012) in Monterey, California.
The presentation was titled "Low Power Design: Is the Problem Solved?" Wang started his talk by noting that power requirements have different drivers in different vertical markets. In the mobile area, the concerns are battery life and cost; in data centers, the concerns are power efficiency and cost of ownership.
"Ideally, I want to do low-power designs from the architectural level down to silicon in a very predictable way," he remarked. "In order to save power, software is king." But what really happens, he said, is more like the chart shown below. There is little visibility during system design. There's no good way to correlate RTL with the final silicon power. Integrating multiple IP blocks from different sources will change the estimation and disrupt the design flow. Finally, if real software doesn't run until silicon is available, many potential power gains can be lost.
There is some good news. Low-power design flows weren't automated 5 years ago, and there was no way to state power intent in a consistent way throughout the flow. Today, with power intent formats including Common Power Format (CPF) and Unified Power Format (UPF), there is a way to express and convey intent throughout the low-power flow.
Further, there are a number of popular low-power design techniques at the hardware level. These include power shutoff (PSO), dynamic frequency and voltage scaling (DVFS), adaptive voltage and frequency scaling (AVFS), multi-supply voltage (MSV), and adaptive body bias. The catch: all of these techniques have a high impact on the design flow.
Linking Software to Silicon
So what's next? "To attack power, software is the first step," Wang said. "However, there is a link between the software and the silicon. Software provides a higher level of abstraction for management and control - you shut off this block, you reduce this frequency. The challenge is that, if the decision you make at that [software] level is not well correlated to silicon, you make the wrong decision."
Thus, the first problem we need to solve is to correlate software and silicon, and to bring forth the accuracy that's needed to make good decisions at the systems level. "There is a huge gap between the accuracy you need and the information that's available at the software level," Wang said.
He suggested three ways to close that gap:
A lot of the potential power savings occurs through software control, Wang noted - for example, the software could shut down or speed up a processor. Emulating this behavior on a hardware platform will result in an accurate power estimation. If software does not "do a good job," then low-power techniques like power gating may not actually save power or, at best, won't operate with maximum efficiency.
In conclusion, Wang said that "power is not a silicon problem. It's not a software problem. It's a whole system problem. We have to look at the problem with a holistic approach. We want a design methodology that's repeatable, scalable and predictable." Wang's presentation is available here.
Note: Wang's talk was part of a session organized by analyst Gary Smith, who opened the session with a chart showing where improvements in SoC power consumption will come from through the year 2026. A recent EDA30 Insider blog post takes a detailed look at that chart. Another EDA30 Insider post reviews Wang's talk. See the list below for other Industry Insights and EDA360 Insider posts from EDPS 2012.
Previous Blog Posts from EDPS 2012
Industry Insights "EDA Symposium: Users Cite 3D-IC Design Tool Needs"
Industry Insights "EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs"
Industry Insights "Is System Modeling the Next EDA Abstraction Level?"
EDA360 Insider "Want a peak at a possible Qualcomm 3D IC roadmap?"
EDA360 Insider "3D preview from EDPS: Qualcomm's Director of Engineering Riko Radojcic talks 3D and 3D EDA"
EDA360 Insider "3D Thursday: A funny thing happened to me on the EDPS 3D-IC Panel"
EDA360 Insider "Software development for SoCs requires "bespoke" software enablement platforms"
EDA360 Insider "Jim Hogan's top six SoC trends for 2012. Want to know what they are?"