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Hardware/software co-development tools such as virtual prototyping, emulation, and FPGA-based prototyping are in use today and are making a difference. That was the message behind a Cadence-sponsored breakfast at the Design Automation Conference (DAC 2012) June 5, where two users described their experiences in person, and three more provided statements by video.
The breakfast also included a Q&A panel discussion moderated by Steve Leibson, marketing director at Cadence. Panelists were as follows, shown left to right below:
Schirrmeister started the session with a discussion of what Cadence has learned from customers about hardware/software co-development. 15 years ago, he noted, chip companies provided just the chip and some low-level firmware. Now they have to provide more and more of the software stack, and they employ a huge number of software developers as a result.
A delay in software development can be devastating. Even a week could impact the bottom line by $10 to $20 million. "Software development needs to be co-designed and co-verified so the overall schedule can be reduced," Schirrmeister said.
Another important point is that no one type of development platform serves all needs. That's why the System Development Suite includes four connected engines - the Virtual System Platform, the Incisive Functional Verification Platform, the Palladium XP Verification Computing Platform, and the FPGA-based Rapid Prototyping Platform. "The idea is to shorten the schedule by several months by getting hardware and software onto a much more parallel path," Schirrmeister said.
Videos Tell the Story
One user video featured David Beal, who is responsible for product marketing for the Xilinx Zynq-7000 Extensible Processing Platform. Last year Cadence and Xilinx collaborated to build a Zynq-7000 Extensible Virtual Platform based on the Virtual System Platform. This platform, Beal said, "allows our customers to develop software before the RTL is complete, even before the applications are complete. The big advantage is that they can create software in parallel with hardware and firmware development."
While many Xilinx customers have never used virtual platforms, many realize that it is a hardware replacement and that it can also provide advanced debugging. "What they sometimes miss," Beal said, "is that a virtual platform adds an additional software development path that wasn't available. Now they can have hardware, software, and firmware flows all in parallel. Time to market can be reduced quite dramatically."
Wai-Chee Wong, senior member of technical staff at Freescale, talked in her video about the Palladium XP. She noted that the emulator is so fast that Freescale can run software applications before taping out the design. Further, engineers can run a power analysis with Palladium, and there's a path from emulation to FPGA-based prototyping.
That statement was a nice segue into a video in which Narendra Konda, director of hardware engineering at NVidia, talked about his company's use of the Rapid Prototyping Platform (RPP). "For many years we had been designing our own FPGA-based prototyping systems," he said. "Recently we started using the RPP from Cadence because it uses the existing infrastructure from Palladium, which we have been using for many years."
Alex Starr - In-Circuit Acceleration at AMD
In May 2012 Cadence introduced a new IC verification use model called in-circuit acceleration. As I described in a previous blog post, it combines the speed of in-circuit emulation with the advanced debug capabilities of simulation acceleration. Starr described why it's needed and how it's used at AMD.
He first described a common scenario. You're running a big workload on the emulator, maybe a 10-hour run, and something goes wrong. You dump some waveforms but miss the failure point. Now you have to reschedule time on the emulator and dump some waveforms again in hopes you'll find the trigger. This process can be repeated several times over.
Starr then described some of the technology behind in-circuit emulation, including the addition of a new clock domain to Palladium, and the ability to connect to a C++ process on the workstation while the rest of the system runs in in-circuit emulation mode. "This effectively gives us full in-circuit emulation combined with the benefits of simulation acceleration and we get no speed degradation whatsoever," he said. "Bugs that typically took weeks of root-cause analysis can now be analyzed in hours."
Chuck Cruse - Rapid Prototyping at LSI
There are plenty of reasons to use FPGA-based prototyping, according to Cruse. "It's a real exercise of the system," he said. "It's close to the chip behavior. It's a great hardware/software integration vehicle once you get it going. It does a good job of detecting real-time issues and clock domain problems."
But it's also traditionally had some shortcomings. First, any delays in developing the prototype reduce its effectiveness. Debug visibility is still a challenge. And, Cruse said, "we need to make sure we can do a quick turnaround with bitstreams and not have a day's worth of compiled synthesis going on."
For years, he said, LSI has been building its own FPGA prototypes, doing all of its own customization including time-domain multiplexing between signals. "RPP should let us automate that," he said. Cruse said LSI engineers want to start with a virtual prototype and go all the way from there to a final hardware prototype. They want to "bring specifications to life in a virtual world, get the hardware and software guys talking to each other, and work through some what-if scenarios before we get to the RTL stage."
Speeding Up VIP
Last but not least, Erik Panu talked about the importance of commercial verification IP (VIP) and the newest addition to the Cadence VIP Catalog, accelerated VIP. This VIP can run 100X to 1000X faster than simulation, depending on use model. This can translate into a 40X speedup over Universal Verification Methodology (UVM) simulation. "People are using different verification environments, and VIP has to be used in different ways," Panu said. "It's critical that VIP runs with the right speed and the right use model."
Some Panelist Questions and Answers
Q: How does somebody get started with all this stuff?
Starr: If you're entering the emulation space, you have to present the case to internal management and be very clear what you expect to get out of it. You have to think, "I can save 2, 3, 4 weeks of time to market and that means millions of dollars for my company." The other thing is that you can start out very simply with a static testbench in Palladium and then work your way up to simulation acceleration or in-circuit emulation.
Q: How do you decide that your RTL is ready for rapid prototyping?
Cruse: The big thing is to show enough functionality to take it to the next phase. An FPGA hardware prototype without our SERDES interconnect is just a lump. Trying to debug that without any real I/O going through the system is extremely difficult. So for us, having a minimal I/O is needed to get to an FPGA prototype.
Q: Can you use assertions instead of a synthesizable testbench in Palladium?
Starr: Yeah, you can use assertions as a way of triggering when you want to dump waves. It's a good way to do it and we're looking to introduce more assertions. You still have the problem of understanding where that trigger point is. But assertions can help.
Q: Can I take a virtual platform model directly to a high-level synthesis tool?
Schirrmeister: A software virtual platform is deliberately written in TLMs that are optimized for high speed and are not synthesizable. We have not figured that out yet as an industry, but we're getting closer.
This was a long and useful discussion with many more questions, but I'll stop here. It's great to hear some user perspectives on hardware/software co-development - and to realize that it's not just talk, it is really happening.
Industry Insights blog posts about DAC 2012
ARM CTO at DAC 2012: The Truth About Semiconductor Scaling
DAC 2012 Panel - Can One System Model Serve Everybody?
DAC 2012: EDA Industry Celebrates 10 Years of OpenAccess
TSMC-Cadence Collaboration Helps Clarify 3D-IC Ecosystem
Gary Smith at DAC 2012: Multi-Platform Design and the $40M System on Chip
DAC 2012 IBM Keynote: Multi-Core Performance Growth Slowing, New Approaches Needed
DAC 2012: How Unified Coverage Interoperability Standard (UCIS) Will Ease IC Verification
DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm
DAC 2012 Panelists Tackle Tough Questions About 2.5D-ICs and 3D-ICs