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At 14nm and below, it's a good bet that many IC designs will use a new 3D transistor technology called "FinFET" (or, to use Intel's term, "Tri-Gate"). With the promise of greatly reduced power at a given level of performance, there's much to like about FinFETs. But there are also a few design challenges and tool requirements that are important to remember.
To better understand the challenges, I recently talked with Vassilios Gerousis, distinguished engineer at Cadence. The challenges appear to be manageable. Manufacturing is not expected to be a big hurdle, and digital designers will see relatively little change. On the custom/analog side, however, transistor-level extraction must comprehend the 3D structures, SPICE models will have added parameters, and a new layout methodology will be needed to improve designer productivity.
The term FinFET was coined by Prof. Chenming Hu and other U.C. Berkeley researchers to describe a new type of multi-gate, non-planar transistor. (Prof. Hu spoke about FinFETs at Cadence last year - for a detailed review, see Steve Leibson's EDA360 Insider blog post). In a FinFET, the FET gate wraps around three sides of the transistor's elevated channel, or "fin." This forms conducting channels on three sides of the vertical fin structure. This approach provides much more control over current compared to planar transistors. Multiple fins can be used to provide more current.
A double-gate FinFET device. (Source: Irene Ringworm at the English Language Wikipedia)
FinFETs took center stage in May 2011 when Intel announced a "significant breakthrough in the evolution of the transistor." The company revealed that its Tri-Gate transistor was going into high-volume production at the 22nm node in a chip code-named "Ivy Bridge." According to Intel, 22nm Tri-Gate transistors provide a 37% performance increase at low voltage compared to 32nm planar transistors, and use 50% less power at the same performance as 32nm planar transistors. Added wafer cost is only 2-3%.
In a FinFET, Gerousis noted, gates turn on and off much faster than with planar transistors, since the channel is surrounded on three sides by the gate. As a result, leakage is substantially reduced. Vdd and dynamic power are significantly lower as well. "In the last several generations of technology nodes, the power supply maintained 1.0 volts," he said. "Now we can go to 0.8V or 0.6V and that helps to reduce dynamic power."
While digital designers will see little change in their design flows from FinFETs - aside from better performance and lower power - custom/analog designers won't get off quite so easily. Physical tools are being changed to support new rules for 14nm and to support new standard cell architectures. Poly gates and fins are new fabric elements that need to be constructed using 14nm rules to create functional standard cells.
One constraint custom designers will face is that all the fins on the transistors on a given chip must be the same width and height. Designers can add fins to increase the width, but this can only be done in discrete increments - you can add 2 fins or 3 fins, but not 2.75 fins. In this respect there's less control over the design than with planar transistors, which can be adjusted to arbitrary channel widths.
Of course, there may be some unintentional manufacturing variation in the width and height of fins. This impacts the drive current and that can affect timing delays, so this variation needs to be modeled and mitigated. Further, metal and via resistance may be a problem, because lower metal layers carry more resistance. Both EM and timing will be impacted by the increased resistance of wire at 20nm and below.
On the tool side, transistor-level extraction must be aware of the capacitance and resistance that arises from the 3D transistor structures. FinFET SPICE models are needed, and they will have additional parameters such as the number of fins. Simulators must be able to interpret these models. Layout tools may need some added knowledge, but Gerousis believes this can be automated.
Like any new semiconductor technology, FinFETs will require an ecosystem that includes EDA tools, process design kits (PDKs), physical IP, and silicon-proven manufacturing processes. Early collaboration between EDA vendors, IP providers, foundries, and semiconductor companies will be crucial. That's why Cadence is actively working with its partners on EDA support, SPICE models, and test chips. "We'll be ready when FinFETs go into production," Gerousis said.
We expect that early customer design engagements could start in late 2013, as foundries release design rules and SPICE models. Ramp-up and yield improvement will come next. Volume production may be late 2015.
So by what time is FINFET expected to be a part of mass production?