Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
The PCI Express (PCIe) protocol is becoming more commonplace and complex, making verification a bigger challenge than before. NVM Express (NVMe), which leverages PCIe to provide an interface to flash-based storage applications, only adds to the complexity. A July 25 EE Times webinar, now available on demand, provides a number of tips for (as the title says) "Shorter, Better, and Easier PCIe and NVMe Verification."
Presented by Gouqing Zhang, verification IP (VIP) CTO at Cadence, and Moshik Rubin, senior product marketing manager at Cadence, the webinar provided hands-on details about the following:
I found the discussion of performance analysis and optimization particularly interesting because, as Rubin said, this is something that is not typically done during the IC verification process. "But we think it should be, especially with NVMe coming into the game," he said. In the webinar, Rubin showed how performance can be optimized as part of the PCIe and NVMe verification process.
An Evolving Protocol
Zhang noted that the cloud revolution and the mobile revolution are placing increasing demands on SoC and system designers -- speed, cost, latency, bandwidth, low power, and resource utilization, to name a few. PCIe has addressed the speed issue by moving from 2.5G transfers/second in its first generation to 8G transfers/second in Gen3, with 16G transfers/second on tap for the emerging Gen4 spec.
Rubin identified several verification challenges. He spoke of the need to ensure that a PCIe core is functional and "bug free" before integration with a higher-level application. A second challenge is to reduce effort and to reuse much of the existing testbench for derivative protocols. A third is to set clear and measurable signoff criteria. The fourth challenge is performance optimization.
Taking IP Verification "Off the Table"
"We keep seeing many design and verification teams struggling with integration," Rubin said. "You need to integrate your PCIe design with some external model or VIP, and you need to know a lot of details of the spec and the IP." What's needed is a dedicated tool that removes the need to learn some of these details. Such a tool would have a knowledge of the protocol and would capture all relevant PCIe related parameters. It would disallow incorrect combinations. (Rubin didn't directly discuss the Cadence VIP configuration GUI, but it was displayed on one of the slides during this discussion. You can read more about it here.)
Creating an Executable Verification Plan
To cope with growing verification complexity, Rubin said that design teams should create an executable verification plan (vPlan) that is linked to the PCIe spec. The vPlan defines the needed testing for each feature, and provides and tracks coverage metrics that can be measured as verification proceeds. Once a comprehensive vPlan exists at the block level, it can be integrated into an SoC view that considers application-relevant scenarios.
Analyzing and Optimizing Performance
Functional verification checks logical bugs only, Rubin noted, "but performance bottlenecks are bugs that are sometimes even more severe than logical bugs." All too often they are exposed late in the process, perhaps in the lab, and they can lead to significant project delays or even cancellations.
The right way to handle this situation, Rubin said, is to use the same infrastructure and testbench to get performance metrics. "You have a lot of information in your VIP, or in your model, about what is going on in the link, and you can abstract the relevant metrics to help you figure out if the design is behaving in an optimal way," he said. For example, the duration of low power states can help analyze power consumption, actual data traffic can provide an estimate of throughput, and queue utilization gives insights into overall resource utilization.
PCIe provides a number of parameters that can help optimize performance. Users can adjust device-level power states, link-level low power states, the number of lanes, and number and depth of queues, and the speed of the link. "The right way to do it is to run different tests with different parameters and see what your performance is," Rubin said.
NVMe Command Processing Flow
Rather than give a generic description of NVMe, the webinar focused on the complex NVMe command processing flow. Rubin walked through this flow and talked about what needs to be verified. It adds up to a hefty list. He pointed to two ways to reduce the effort. One is to use a "strong infrastructure" that enables control of all NVMe/PCIe functionality, including error injection and corner case scenarios. Another is to create an executable verification plan and to use it to track progress.
Cadence offers PCIe and NVMe VIP, and recently added a performance measurement utility to its PCIe VIP. For further information about Cadence VIP, see the Cadence VIP Catalog. To access the on-demand EE Times webinar, click here.