Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
In the semiconductor design flow, engineering change orders (ECOs) are as inevitable as death and taxes. While this has always been the case, ECO timing closure is becoming increasingly difficult as the number of operating modes and process-voltage- temperature (PVT) corners skyrockets. What's needed is a new "physically aware" MMMC ECO timing closure flow.
I recently talked to Ruben Molina, product marketing director for timing signoff at Cadence, about the limitations of the traditional IC timing closure flow. He noted that today's flows are typically comprised of point tools. You run one tool, export a file, and then go to the next tool. Eventually you get a timing report and you have to figure out how to fix the violations.
Of course, changing anything in the layout can cause new timing problems, so many ECO loops may be needed. The following diagram illustrates some of the challenges of the traditional flow.
Figure 1 - A typical timing closure flow
Molina observed that closing a design often takes 10 or more ECO iterations. "Those iterations can last anywhere from a day or two to several days. It could be a week. Add it all up and anywhere from one month to two or three months is spent in this final timing closure phase."
Too Many Views
One reason timing closure takes so long is that as process nodes shrink, there are more and more "views" to consider. A "view" is a combination of a mode (say, functional mode "1") and a corner (such as worst-case temperature) that is required for a particular timing check, such as setup or hold. A quick look at theoretically possible corners shows how quickly things can add up:
Multiply this out and you get 3X3X5X5=225 corners. And that's not even considering operational and test modes. Throw in 6 modes and you're well over 1,000 views. At 20nm, by the way, modeling mask shift variation due to double patterning could increase extraction corners by as much as 3X.
In practice, as Molina points out, design teams don't run timing analysis and optimization over every possible view. At 28nm, for instance, a design team might look at 16 operational corners. The total number of views for signoff might be in the 64 to 128 range. In implementation, however, this number may be reduced to 8 or 16 to keep things manageable.
A New MMMC ECO flow
So what's needed to make MMMC timing closure more manageable? One requirement is an MMMC analysis solution that can scale with an increasing number of views. And one way to handle this is to run multiple views in parallel using distributed processing in a compute farm. (For example, the Cadence Encounter Timing System supports both distributed processing and multi-threading.)
Another approach is to leverage "commonalities" between the modes and corners, and avoid repeating tests that might not be necessary. For example, if there are no failures at a worst-case corner, it might be safe to assume there will be no failures at a nominal corner.
Most important, however, is an MMMC ECO flow that is physically aware. This means that the ECO file that is written out not only represents logical changes in the netlist, but also specifies the coordinate information for where cells should be placed. As a result, Molina said, "we know where all the vacancies are in the design, and we know that if we locate a cell in a given location, it will go exactly where we want it to go. If we fix 100 violations, then 99 will still be fixed after implementation."
As shown below, the Cadence MMMC timing closure signoff flow is physically aware. It leverages the Encounter Digital Implementation (EDI) System for layout optimization, QRC Extraction for multi-corner extraction, and Encounter Timing System for MMMC static timing analysis, all without external file transfers. "For a design that has tens of thousands of hold violations, we are able to fix 99% in one iteration, which is an overnight run," Molina said.
Figure 2 - Cadence offers physically-aware MMMC timing closure signoff flow
This flow can fix hold and design-rule violations today, and upcoming versions will provide automated fixing for setup violations, glitches, and leakage. The "holy grail," Molina said, is to reach a point where there is no need to export an ECO file, because ECOs will all be handled automatically in the implementation tool. "We are in the first evolution of what will eventually become a completely automated signoff quality optimization within a single-step IC design flow," he said.
what are the cases available in MMMC ..i had seen WCC also as a case ...what is meant by wcc case..