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Do you want to enjoy the benefits of formal verification without having to become an expert? A newly archived Cadence webinar shows how you can do just that, using assertion-based verification IP (ABVIP) that supports both formal and dynamic verification of systems-on-chip using the ARM ACE protocol.
The webinar is titled "ACE Assertion-Based Dynamic, Formal, and Metric-Driven Verification Techniques with ABVIP." It shows how ABVIP fits into the protocol compliance flow, how it includes support for assertion-driven simulation, how the debug interface works, and how to use ACE ABVIP together with Universal Verification Methodology (UVM) ACE UVC components.
Joe Hupcey III, product managing director, began the webinar by noting that many engineers are wary of formal and assertion-based techniques. They don't want to learn an assertion language, they think formal tools require experts, and verification leads have trouble showing the value of assertion-based verification (ABV) in the context of a full project. "You want to quickly install, configure, and verify a standard protocol and move on," he said.
Cadence provides ACE protocol verification as a "formal app" on top of the Cadence Incisive Formal Verifier or Incisive Enterprise Verifier. As described in another recent webinar, a "formal app" meets these criteria:
Joerg Mueller, staff solutions engineer, showed how ABVIP works with a protocol compliance flow. ABVIP provides pre-validated interface properties for validation of interface protocols. You instantiate the ABVIP and connect it to the device under test (DUT) interface. The ABVIP then provides checks and constraints for protocol compliance, and supports other functionality, such as white box assertions or functional assertions inside the DUT.
Coherent Verification IP
ACE stands for AMBA 4 AXI Coherency Extensions. It enables full cache coherency between processors, which is essential for multi-core SoCs. Cadence ACE ABVIP includes these features:
Support for assertion-driven simulation is a key feature. In this use model, simulations are based purely on properties, or constraints. This allows environment visualization and deep bug hunting.
Mueller showed how to instantiate ABVIP for both masters and slaves, and noted that the ABVIP automatically sets up assertions and constraints correctly by instantiation. He discussed debugging using the SimVision interface, and showed screen shots of the ACE waveform layout, transaction-level debugging, signal-level debugging, and ACE transaction tables. The tables, which work for any protocol that uses pipeline transactions, list transactions in progress and also show transaction details and status.
Joining Formal and Simulation
Next, Mueller showed how to run a UVC and ABVIP in concert, using the same verification plan and generating metrics for both simulation and formal verification. Basically, you instantiate the ABVIP with UVC, create a "passive" test, and replay all formal witness traces in the passive UVM environment. This yields information about UVM scoreboard failures, UVM covergroups, and simulation code coverage. You can bring metrics back into the Incisive Enterprise Manager and translate the formal metrics into simulation metrics.
Mueller presented a customer case study that was an early version of an ACE-based design. It used 7 ABVIPs and 7 formal scoreboards. Designers found 22 assertion failures. In one week, they found three critical issues, including one that could have been found only by formal verification.
Mueller concluded with a demo that showed how to configure and run ABVIP, verify protocol compliance, use assertion-driven simulation, and use protocol-aware debugging. And you don't need a PhD in formal verification, or a knowledge of any assertion language, to follow it.
Cadence Community members can access the webinar here (and you can also sign up via this link if you're not yet a member).
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