Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Custom/analog designers working at FinFET process nodes are going to need all the help they can get. As announced by Cadence today (July 8, 2013), TSMC will help out by providing native SKILL-based process design kits (PDKs) for the TSMC 16nm FinFET process. TSMC is also expanding its usage of the Cadence Virtuoso platform to design its own semiconductor IP.
SKILL is a programming language that is used to develop PDKs and PCells (parameterized cells), and is also widely used by customers to customize Cadence tools including the Virtuoso custom/analog and Allegro PCB design platforms. The first 16nm PDKs that TSMC issues will include SKILL-based PDKs.
PDKs link process technology to design, and are an essential part of any foundry-based IC design and manufacturing flow. The diagram below provides an overview of what PDKs contain and how they interact with design tools.
According to Steve Lewis, product marketing director at Cadence, the native SKILL PDKs will unleash the full power of Virtuoso for 16nm design. PDKs, as he explained, contain basic transistors and design rules. But there's also a layer on top of those elements that "has to be able to trigger tools to do the right thing." For non-SKILL PDKs, this layer will typically be written in Tcl, which is different from the language used by the tools, resulting in a disconnect and preventing deeper customization. For SKILL PDKs, this layer will be written in SKILL, providing direct access to Virtuoso.
Specifically, the SKILL PDKs will allow designers to take full advantage of Virtuoso's advanced layout and routing features, including those in the January 2013 Virtuoso Advanced Node release. This release provides such capabilities as color-aware double patterning, "partial layouts" that account for layout-dependent effects, and new local interconnect routing layers. The new PDKs will also enable features such as auto-alignment, automatic handling of design rules during abutment, chaining devices, and advanced routing. "Customers will not have to do a lot of tinkering to use these advanced features," Lewis said.
Lewis noted that there's an exponential explosion of design rules at 16nm. These include a number of positioning rules that depend on the layout context. With the SKILL PDKs, he said, 16nm design rules "will be understood by our router right out of the box. The native SKILL PDK allows the tools to read those rules, digest them, and direct the customer to avoid violating rules as they're doing the layout."
Finally, Lewis noted, TSMC's use of Virtuoso for its own IP benefits Virtuoso users. TSMC and Cadence have cooperated to develop a flow that is proven through TSMC's IP development and silicon. There is also more security for Virtuoso users. "You're using the tool that your foundry provider used to develop the PDK, and that the foundry provider is using for their own designs in their own fab," Lewis said. "If TSMC believes in [Virtuoso], then you as a customer should, too."
Further information is available here.
Related Blog Posts
Introduction to Cadence Virtuoso Advanced Node Design Environment
Ten Things You (Probably) Didn't Know About SKILL