Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
If you're working on the design of mobile devices, the emerging PCIe over M-PHY (M-PCIe) standard could become very important to you. And if you'd like to learn more about it, a recently archived Cadence webinar explains what M-PCIe is, what applications will use it, how it differs from PCI Express (PCIe), and what Cadence offers in support of system-on-chip (SoC) design with M-PCIe.
The webinar was presented June 28, 2013 by Arif Khan (right), product marketing director for the SoC Realization Group at Cadence. (Khan is also a Cadence blogger, and he recently wrote about how Cadence was the first company to demo a complete M-PCIe PHY and controller solution at the recent MIPI and PCI-SIG conferences).
Khan began the webinar with a look at the evolution of PCIe. This protocol, he noted, provides a scalable, high-performance I/O interconnect for computing and communications applications. It started in 2002 with PCIe Gen1, which provides up to 2.5 GT/s. In 2006, Gen2 raised this performance to 5 GT/s, and in 2010 Gen3 claimed 8 GT/s. In 2011 PCIe Gen4 was announced (16 GT/s), but the spec is not yet complete.
PCIe is widely used in applications such as storage, networking, supercomputing, test equipment, and FPGA-based systems. But it is typically not used for mobile applications because of its power consumption. That's where M-PCIe, introduced in September 2012 by the PCI Special Interest Group (SIG) in cooperation with the MIPI Alliance, comes in.
Best of Both Worlds
Basically, M-PCIe combines a PCIe controller with the MIPI M-PHY. It extends PCIe I/O benefits to mobile devices such as tablets and smartphones. As Khan explained, M-PCIe leverages the best of both PCIe and MIPI. And both have benefits. PCIe, for example, is supported in all major operating systems, has a good power management architecture, provides a well developed software model, and offers robust discovery and configuration.
M-PHY offers lower power than the PCIe PHY, better EMI characteristics, and independently scalable receive and transmit channels. This last point deserves some explanation. As Khan explained, download bandwidth on the receive path is always higher than upload bandwidth on a transmit path because a user typically downloads more data than he uploads to a server. M-PHY handles this "asymmetry" very well, and with M-PCIe that benefit is extended to PCIe.
Typically, adopting a new protocol poses some hurdles, but these are minimized with M-PCIe. The transaction and data link layers are handled by a silicon-proven PCIe Gen3 controller. M-PHY silicon has been proven in many nodes. One thing that has to change, however, is how the controller talks to the PHY layer. The PCIe PHY typically uses the Intel PHY Interface for PCI Express (PIPE). The M-PHY, on the other hand, uses the Reference M-PHY Module Interface (RMMI).
Therefore, a new PHY logical layer is required for RMMI, and the PCIe Link Training Status State Machine (LTSSM) must be significantly changed. Clock tolerance compensation needs to be added for M-PHY. The M-PHY supports a number of MIPI protocols, each with its own tolerance; it does not have the standard PCIe clocks of 125, 250, and 500 MHz. In the webinar, Khan provides more information about what needs to change.
Making it Real
In March 2013, Cadence announced the first commercially available design IP and verification IP for M-PCIe. Cadence was also very active in the PCI-SIG working group and is a sponsor of the M-PCIe Engineering Change Notice (ECN).
Khan showed the following diagram of the Cadence M-PCIe IP solution. He noted that the bandwidth is scalable from 1-8 lanes on M-PCIe and from 1-16 lanes for standard PCIe. It supports high-speed gears 1-3, and the client interface is anywhere from 32 bits to 128 bits based on the application. A number of tunable parameters is available. Root port, end point, and dual mode (allowing either root port or end point) configurations are available.
You can access the webinar here. A Cadence log-in is required (quick and free registration available if you don't have one). A "deep dive" M-PCIe webinar is planned for the future. Meanwhile, the following Cadence blog posts have further information about M-PCIe:
Cadence First to Demo Complete M-PCIe PHY and Controller Solution at MIPI and PCI-SIG Conferences
M-PCIe - The New Big Thing from MIPI Alliance and PCI-SIG