Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Memory built-in self test (MBIST) is a design for test (DFT) methodology that has been around for many years. But until now MBIST algorithms have generally been hardwired -- they can't be changed once the design has been built. A new methodology available in the Encounter Test 12.1 release, programmable MBIST, promises to give IC designers much more flexibility.
While programmable MBIST provides benefits at any process node, it is especially helpful at 28nm and below, and will be extremely valuable for upcoming FinFET technology nodes, according to Bassilios Petrakis, product marketing manager for Encounter Test. With sub-20nm complexity, he observed, "you want to be able to adapt the algorithm depending on the situation you have."
"For a new node and technology (transistor) structures, you don't always know what the failures are going to be, or what type of [test] algorithm is really optimized for the technology," said Patrick Gallagher, architect at Cadence. "You can go in with a set of canned algorithms, but if you're getting failures you can fine-tune those algorithms [with programmable MBIST] to something very specific for your technology and your memory design." This level of flexibility allows designers to adapt to the problem at hand.
Building Block Approach
The silicon-proven programmable MBIST architecture allows users to load new algorithms with no penalty. "Algorithms are more than just programmable, they are user defined," Gallagher said. "And we have built in syntax so you can describe to the application how you want the algorithms to run, and you can create any algorithm you want."
The programmable MBIST also comes with 30-40 predefined algorithms that are built into the application. These can be converted into hardwired algorithms to save area - just like the programmable algorithms and the user-defined algorithms, as shown below. Conversely, predefined algorithms can be reprogrammed and run through a JTAG interface. Whether hardwired or JTAG, the tests will run at speed.
A collection of algorithmic "building blocks" allows the programmability. For example, a user could pick a given "march" algorithm that runs 1s and 0s through a memory address space. Users can change backgrounds, sequences, address increments, and more. The illustration below provides an example.
The programmable MBIST building block structure is shown below. Each block can be shared for different levels of flexibility and performance tradeoffs. One Algorithm Memory Unit (AMU) can be shared across multiple Sequence Iterator Units (SIUs), which can be shared to test multiple memories. These shared components pose no limitation on the testing of the memories, except for physical limits. Tests can be done in parallel or serial even with shared components.
Sharing the Data Compare Unit (DCU) involves a tradeoff. The DCU can be shared across multiple read ports and memories, but designers will trade off area for test time, forfeiting what can be tested in parallel for area savings.
One benefit, said Gallagher, is area savings. "We have found that we're getting another 15% to 20% area reduction on top of our standard offering for the same functionality, so we're getting more functionality with less area."
Gallagher noted that the programmable MBIST architecture reads in "memory views," which describe the memory in terms of port descriptions, address manipulation, physical structure, and redundancy structure. Cadence is working with memory vendors on generating memory views.
A "configuration file" contains the information about how to test the memories, and contains the directives that control the insertion of programmable MBIST logic into the netlist. It describes how the targeted memories must be tested, provides information needed to construct the programmable MBIST building blocks, and creates a test plan.
An upcoming Encounter Test release will provide a direct access method for programmable MBIST. Going beyond today's JTAG access method, this provides a minimal pin support solution for the programmable MBIST, which is often required for mixed-signal designs where digital pins are at a premium. JTAG access will still be needed for programmable support.
The programmable MBIST capability can be used at any process node. A Rapid Adoption Kit is available at support.cadence.com to help customers test drive or ramp up on this technology. Gallagher described programmable MBIST in a presentation at CDNLive Silicon Valley 2013. To download the presentation, click here for CDNLive proceedings (Cadence log-in required). After you've logged in to the proceedings, select "Front End Design" and look for session FED105.