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The Large Hadron Collider (LHC)—the largest and highest-energy particle accelerator ever built—has been called "one of the great engineering milestones of mankind." And part of that engineering effort is still going on, as electronic engineers at CERN (European Organization for Nuclear Research) and collaborating universities design mixed-signal ICs to support various experiments that particle physicists run on the LHC.
Built over a 10-year period from 1998 to 2008, the LHC consists of a 27km (17-mile) ring of superconducting magnets and accelerating structures that boost the energy of particles. Inside the accelerator, two high-energy proton beams travel at nearly the speed of light until they are made to collide. Beam energy reaches 4TeV (tera electron volts), and this will be increased in 2015 when the LHC re-opens following an upgrade that is currently taking place.
The purpose of the LHC is to get as close as possible to the conditions in the early universe, immediately following the Big Bang. In 2012, two LHC experiments detected a new particle that was shown to be the long-sought Higgs boson, which is pivotal to the standard model of particle physics and will help explain how elementary particles acquire their mass.
The experiments that are run on the LHC require instrumentation, which is why the CERN engineering department has a group of around 40 micro-electronics engineers who design analog and mixed-signal ASICs. Kostas Kloukinas, shown in the photos, is one of these engineers. In a recent interview, he explained why CERN designs its own chips, the challenges of chip design for high-energy particle physics, and CERN's collaborative design efforts with universities and research institutes.
He also explained how Cadence design services developed a mixed-signal design kit that permits CERN and its collaborators to share common design flows. The flows are based on Cadence Virtuoso tools for custom/analog design and Cadence Encounter tools for digital implementation, in addition to the OpenAccess database. "Our design flows are based primarily on Cadence tools," Kloukinas said. "What we have done with the design tool selection is that, for specific design flows, we have reduced the number of tool vendors to a minimum to increase workflow consistency."
Chip Design for Particle Physics Poses Challenges
CERN develops ASICs for functions such as gigabit optical links, amplifiers, digital readouts, and pixel imagers for particle detectors. These ASICs fill specific needs for scientific experiments. Most are custom/analog or mixed-signal designs, with digital circuitry typically no more than a few hundred thousand gates, although some of the pixel imagers have over a million gates. The CERN micro-electronics group has been working with CMOS processes at 250nm and 130nm, and is now transitioning to 65nm.
These chips may not be using advanced process nodes, but they pose plenty of challenges. For one thing, the signal pulses found in particle physics do not appear in commercial applications. "There is a lot of signal processing that is very specific to particle physics, and you cannot find such signal processors in the industry," Kloukinas said. And this is why, he noted, CERN designs its own ASICs rather than using off-the-shelf ICs.
Radiation hardness is another challenge. Radiation doses in the accelerator may be a few hundred million rads over the period of an experiment—far more than the dose you would get in a spacecraft, and well beyond the typical tolerance of a rad-hard microchip. CERN engineers and their collaborators use a number of design techniques (such as strategic placement of guard rings) to counteract the effects of radiation. They also triplicate logic inside state machines. If one state machine goes out of synch, the other two will bring it back.
As it is elsewhere, mixed-signal integration is a challenge. "As time goes by, we are integrating more and more functionality on the same bit of silicon, so we are moving towards SoCs," Kloukinas said. One function that is frequently integrated is the amplification of very-low-power signals. "We are talking about a few hundred electrons of signal," he said. "In the physics community we do not use millivolts or microvolts, we use the number of electrons."
Finally, low-power design is a must. If circuitry consumes too much power inside a detector, Kloukinas noted, this will require hefty power delivery cabling as well as bulky thermal dissipation systems, thus impairing the quality of physics measurements.
Kits, Flows, and Collaboration
Five or six years ago, the CERN micro-electronics group approached Cadence design services in Paris and asked Cadence to prepare a mixed-signal design kit and mixed-signal design flows that would fit with their methodologies. "We worked together for a few months, and then they delivered a mixed-signal design kit and flows, and they also came to CERN for training," Kloukinas said. "In fact we had 10 training sessions over a year and a half to train in-house personnel and people from universities."
The design kit included a Physical Design Kit (PDK) and digital standard cell libraries, including rad-hard cells. Why not just use PDKs straight from the foundry? Kloukinas said CERN engineers have struggled with a number of "inconsistencies" when they have tried to use separate analog and digital PDKs, and have had a hard time with analog/digital integration. The kit helps resolve those inconsistencies, and the design flow is an added value.
CERN delivers the design kit to their university and research institute partners, providing a sort of common platform for mixed-signal IC design. CERN's main role, Kloukinas said, is to co-ordinate the work rather than do all the work. For example, a university group might develop a laser driver for a gigabit optical link. CERN might design a Reed-Solomon decoder for that link, and another university or research institute might build a pin-diode amplifier. Typically CERN will do the chip assembly in house, although in some instances they have used Cadence design services.
The design flows accommodate both analog-on-top and digital-on-top methodologies. The flows include the Virtuoso family of custom/analog tools, the entire Encounter suite of tools, and Cadence Incisive SoC verification tools. Both analog and digital tools use the industry-standard OpenAccess database.
In the analog-on-top methodology, for example, a designer can develop a floorplan in Virtuoso, export it to Encounter for digital block implementation, and bring everything back into Virtuoso for chip finishing (see diagram below). "With OpenAccess, we can go back and forth between Virtuoso and Encounter very fast," Kloukinas said.
Source: 2011 CDNLive EMEA presentation by Kostas Kloukinas, CERN
To provide a consistent database among numerous designers, CERN uses the SOS data management software from Cadence partner ClioSoft. In a recent EDN article, Cliosoft engineers detail how their company's software aided in the development of the FEI42, an imaging chip for a hybrid pixel detector for ATLAS, one of the main particle detector experiments at the LHC.
To save money on the fabrication end, CERN uses commercially available CMOS processes and takes advantage of multi-process wafer (MPW) services.
On February 14 2013, the CERN LHC ended its first running period, which started March 30, 2010 with the first collisions at 7TeV. The LHC's first run has seen major advances in physics, including the discovery of a new particle, the Higgs boson, announced July 4, 2012. The LHC and the experiments around it are now undergoing planned upgrades for two years. In 2015, LHC is expected to run at twice the energy and with even more intensive beams. It will continue the search for new particles and phenomena that can explain the basic laws of nature and how the universe came to be the way it is today.
The LHC is about as far from a consumer mobile application as you can get. But it's a great illustration of the importance of a consistent methodology, flows, and tools among geographically disparate design teams, especially in the challenging mixed-signal realm.