Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Cadence this week (May 19, 2014) is announcing the first DDR4 PHY IP built on TSMC's 16nm FinFET process. The 3200Mbps DRAMs that can take best advantage of this capability aren't shipping in volume yet - but you can "future-proof" your 16nm SoC design by using a DDR4 controller and PHY that can scale up to 3200Mbps as the parts become available. Further, the availability of 16nm FinFET support for very high-speed memory might provide yet another incentive for considering that process node.
DRAMs today are available at 2133Mbps, a speed supported by both the DDR3 and DDR4 standards. You can easily get this performance in a 28nm process. (Cadence, in fact, announced in January that its DDR4 PHY IP achieves 2667Mbps in 28nm). But according to Kishore Kasamsetty, product marketing director at Cadence, you really need to go to a FinFET process to get 3200Mbps performance.
And who needs that performance? The first adopters will probably be enterprise applications such as servers, network switching, and storage fabrics. These applications can also take advantage of the overall power, performance, and area advantages of a sub-20nm process.
"We don't know exactly when DRAMs rated higher than 2400Mbps will go into high volume, but if you're designing today on an advanced process using IP optimized to take advantage of the higher performance offered by the FinFET process, you are set for the future" with the Cadence DDR4 PHY, Kasamsetty said.
As he pointed out, you don't want to have to redesign your DDR4 PHY interface when the new parts come out. Even if your application needs only a maximum of 2400Mbps performance today, the Cadence PHY IP that's capable of 3200Mbps operation will provide additional robustness and improved system margins. As the application needs increase, and higher speed DRAMs are available, designers can reuse the same DDR PHY IP without having to do a costly redesign or procure new IP.
A Long Time Coming
Although JEDEC began work on a successor to DDR3 around 2005, the JEDEC DDR4 standard was not published until September 2012. Compared to DDR3, DDR4 offers higher performance, greater reliability, reduced power, higher capacity, a more robust RAS (reliability, availability, and serviceability) feature, and better die stacking capabilities. DDR4 potentially provides 50% more bandwidth and 20% less power than DDR3.
The JEDEC web site cites the following DDR4 features:
For a deep dive into DDR4, you can purchase presentations from the February 2013 JEDEC DD4 workshops.
Not all PHY IP is created equal. The Cadence DDR4 PHY IP works with Cadence DDR4 controller IP, which is a soft IP block. The controller has, however, been updated with pipeline and speed improvements to support scaling up to 3200Mbps. Here are some key features of the 16nm-enabled Cadence DDR4 PHY:
Both the Cadence DDR4 controller and PHY have been verified in silicon from TSMC's 16nm FinFET process. Previous to the 16nm FinFET support, the Cadence DDR PHY IP has had a 10-year history of use (originally with Denali Software) and has been extensively validated with multiple hardware platforms.
A Video Overview of DDR4
In a recent Whiteboard Wednesdays blog post, Kishore Kasamsetty provides a history of DDR4 technology, and reviews the power and bandwidth improvements of DDR4 over DDR3. He also discusses the memory standard's specifications and the engineering challenges of meeting those specifications. Finally, he presents requirements for the DDR4 controller and PHY.
A datasheet for the 16nm-enabled DDR4 PHY is located here.