Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
After listening to a Design Automation Conference (DAC 2014) keynote speech last week by Karim Arabi, vice president of engineering at Qualcomm, I have a lot more respect for my smartphone. In his keynote, Arabi detailed a number of tough challenges facing designers of mobile computing platforms such as smartphones.
Arabi's speech was titled "Mobile Computing Opportunities, Challenges, and Technology Drivers." During the speech, he appealed for EDA innovation to stem a slowdown in process node scaling. He knows EDA well, having co-founded an analog automation startup, Opmaxx, in the 1990s.
"I know how difficult the EDA industry is," Arabi said. "This is an industry that works really hard to enable wonderful solutions. It's hard to imagine where we'd be without EDA."
Mobile computing creates a new world
"Mobile computing is the largest technology platform ever built by mankind," Arabi declared. "Today there are an estimated 7 billion connected devices out there, while the whole population of the Earth is about 7.3 billion." And 25 billion devices are expected by 2020, he noted.
There is a corollary to Moore's law in the mobile business, Arabi said—an expectation that data density should go up by 2X every year. That's about 1000X over a ten-year period. "We set our goal at Qualcomm to enable the 1000X challenge," he said.
In 2013, Arabi noted, smartphones generated 49X more data traffic than basic phones. While early cell phones were used mostly as phones, smartphones today are primarily used for pictures, videos, and emails. By 2017, it is estimated that 2/3 of mobile traffic will be video. This takes a lot of computing and a lot of storage—and the place to find both is in the cloud, which Arabi said goes "hand in hand" with mobile computing.
The always-on challenge
Your smartphone knows a lot about you. It knows your travel plans and it knows when you're driving to work. Arabi observed that smartphones "can collect information and anticipate what you are about to do. They can arrange your experience and optimize it based on that. But that means a device has to be on all the time."
Always-on, always-aware devices demand ultra-low power. They also require some architectural changes. "The mobile architectures we have are not enough to enable always-on, always-aware," Arabi said.
Network challenges and drivers
Arabi said that Qualcomm has adopted three strategies to maximize network performance for mobile devices:
"With these three strategies," Arabi said, "we are on track to sustain 2X data growth every year."
Optimizing mobile devices
On the device side, designers must aggregate many different technologies in one device. Computing, connectivity, sensors, voice recognition—"all these are good technologies, but they become a challenge because now you have to aggregate a wide array of different technologies on the same chip, and it has to be extremely low power."
A heterogeneous computing approach is needed, and that means different kinds of processors on the same chip. As Arabi noted, some applications prefer CPUs (2D-3D video conversion), some prefer GPUs (image processing), and some prefer DSPs (character recognition). The quest for power efficiency is driving demand for customized accelerators. Arabi showed how Qualcomm has come up with a 1080p video engine that allows an 8X power reduction.
Mobile devices have historically lagged PCs in performance, but are now at par or exceeding PCs, according to Arabi. But form factors are very small, and one result is a "crisis" in power management. Thermal management is a big concern as well, both from the standpoint of junction temperatures and "skin" temperatures. "We have to manage performance, power, and thermal at the same time, or we leave performance on the table," Arabi said.
Here are some of the other challenges that mobile device designers are facing:
Solutions—3D-IC, memory, and embedded voltage regulators
Arabi's talk covered solutions as well as challenges. 3D-ICs have been touted as a potential solution for interconnect problems. But through-silicon via (TSV) architectures are not really solving the interconnect issue and are costly, Arabi said. Qualcomm is looking at "monolithic" 3D-ICs that use normal vias between stacked dies. This can provide a one-process-node advantage along with a 30% power savings, 40% performance gain, and 5-10% cost savings.
Embedded memory needs a lot of work with respect to power, density, and reliability. MRAM (magneto-resistive RAM), which is based on the "spin" of electrons, is a possible solution. Arabi noted that MRAMs provide non-volatile memory and that leakage current is very low. However, speed is still a problem.
Finally, in addition to conventional voltage islands, Qualcomm uses embedded voltage regulators to save power. These enable more granular voltage islands, faster supply current transitions, reduced margins to account for voltage drops, and also better performance, Arabi said.
A plea for EDA innovation
With node scaling slowing down, mobile device designers are looking to the EDA industry for help. "EDA enabled this [mobile] industry, so it is time for EDA to boost its innovation cycle to compensate for this slowdown," Arabi said. However, he noted, most of the major innovations in EDA technology happened in the 1980s and 1990s rather than recently.
Arabi said the following EDA innovations will be required by 2020:
"We really need more innovation, and I think these things are possible," Arabi concluded. "I think we have some of the best talent in the world in the EDA industry."
Related blog posts
- Gary Smith at DAC 2014: How System Design is Changing Electronics
- DAC 2014 Keynote: Imagination CEO Charts New Opportunities for Semiconductors
- DAC 2014 Dual Keynote: How Automobiles are Getting Smarter
- DAC 2014 Keynote: EDA Can Tap Into New Revenue Streams
Many of Karim Arabi's requests for innovation are achievable now, if the right methodology and tools are lined up. The cycle time requirements have to be achieved by a focus on more optimal results, a so-called 'shift to the left' that many including Frank Schirrmeister of Cadence have written and spoken on. Get things right at a higher system level in order to have a tighter focus downstream to transistors. The virtual prototyping technology at Cadence (models and IP; simulation and emulation technologies) is a major shift to the left. Going further left, further upstream, the 'seamless hardware/software co-design' can be found outside of Cadence in Space Codesign's next generation ESL technology that can retarget functions in your application for either hardware or software implementation. As a design creation front-end, promising candidates with optimal hw/sw partitions can (in theory, on the back of a napkin so to speak!) be mapped into the Cadence environment for more detailed analysis and verification, and onward in the ASIC flow.