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High-level synthesis (HLS) is an emerging IC design technology that promises huge productivity gains, but you need to understand its advantages and limitations before diving in. The best way to get that understanding is to listen to the experiences of engineers who are using it - and a panel discussion at the recent Design Automation Conference (DAC 2014) provided a good venue for doing just that.
The panel was titled "Who Drives Whom? High-Level Synthesis or IP Reuse?" It was organized by Brett Cline, sales director at Cadence, and former vice president of marketing and sales at Forte Design Systems (acquired by Cadence in February 2014). The moderator was Warren Savage, CEO of IPextreme. Panelists were as follows, shown left to right in the photo below:
Panelists first gave opening statements about their HLS experience, as follows:
Gunasekara - IP Startup Perspective
Gunasekara started NGCodec, a startup focusing on H.265 video IP, in 2012. "As a startup, it was really important that we did something different. We looked at the tools and the capabilities and we were willing to take a risk [with HLS]." As a startup, NGCodec does not have a lot of legacy RTL code to contend with. "It's still early days, but we think we can benefit from many advantages that HLS offers."
Rawat - Intel's Interest in HLS
Rawat is responsible for bringing new EDA technology into Intel, and he noted that "we have been very interested in high-level synthesis for quite a long time." Return on investment, he observed, is based on the methodology you use.
Garrett - HLS Enables Reuse
Garrett's group is tasked with working on "hard problems" at Broadcom. He noted that Broadcom has a very aggressive tapeout schedule and needs to quickly tape out variants of existing chips. "HLS has the ability to take a very stable design and tweak it and move into a slightly different space," he said. "We can keep 90% of the code common and get a vastly different architecture."
Garrett noted that HLS can retarget a design while optimizing it to the target frequency that the customer needs. "This is really the high-level goal of reuse - to not redesign the wheel, but to make sure the technology is optimal at every point."
Q: Everyone has mentioned benefits, but HLS has been around for at least a decade. What held it back? Is adoption increasing?
Gunasekara -- "The key word is legacy. So often, you are modifying or improving an existing block. It's very rare to have a clean sheet of paper."
Rawat - "For any design team, a new approach takes a few iterations to get right. Are you willing to go through those iterations?"
Garrett - HLS starts with a high level of abstraction, and produces an "unreadable" gate-level netlist. So teams on the back end lose control because it's not easy to make changes. "Designers have to trust the [HLS] output, and I think the trust is starting to be there."
Q: There are also organizational hurdles to adoption. What are the tradeoffs?
Garrett - "It's a whole new level of abstraction to get into C++. You have to understand fixed-point types and design at that level." Do you take systems people who can write C code and bring them into hardware design, or do you take RTL people and bring them up to C++? "There is resistance from both sides. We've got to meet in the middle somewhere."
Rawat - "The maximum cost today is verification. Most hardware companies today are selling not just the component, but a whole bunch of software on top of it. You need a system that allows you to verify hardware and software, and if hardware is written in RTL it's not going to work."
Gunasekara - "There is a learning curve. We're going to take a little longer in the first release, but we really do believe that the flexibility HLS gives us is worth that."
Q: If you have both legacy RTL code and HLS, how do you make the transition?
Rawat - Designs today are putting more and more components on chip. "The trick is to figure out who's trying to put new stuff in there and doesn't have legacy code, and would like to get something developed yesterday."
Gunasekara - We have had discussions with customers about delivering HLS code [SystemC] as opposed to RTL, and most are "reasonably comfortable." Engineers like to try new things, but not in the middle of a 16nm tapeout.
Q: What is the single biggest pain point that remains with the tools?
Rawat - "Debug in the HLS flow is the biggest pain point." With SystemVerilog or Verilog RTL, many simulation, emulation, and debugging tools are available - but that is not yet the case with HLS.
Garrett - SystemC is often based on fixed-point data types, and that slows simulation speed. When you have a threaded simulation, it's really painful to debug. You might need to resort to printf statements.
Gunasekara - Feedback and visibility. "When things don't work, it is not so easy to figure out why."
Q: Where would you not use high-level synthesis? (I asked this)
Garrett - It's not good for very-high speed design, where designers can push the last flip-flops and craft the pipeline stages. HLS moves pipeline elements around and adds extra protocols, and there's a penalty. However, control-intensive logic is getting better with HLS. "But when you get very complicated protocols, these get challenging."
Rawat - HLS is not helping with analog/mixed-signal portions of the design. Also, where designs have very deep pipelines, "it is difficult to see how HLS can partition all of them and get it right."
Q: When you go to HLS, do you bring software designers into hardware design, or bring RTL hardware designers up to HLS?
Gunasekara - We try to hire people who can work with both hardware and software, but we've had more success with hardware people than with software algorithm designers.
Rawat - Pairing software and hardware designers is probably the right thing. "Sit them down together and let them work it out, and get expertise on both sides."
Related Blog Posts
How Cadence Acquisition of Forte Boosts High-Level Synthesis
High-Level Synthesis Users: Productivity Gains Beckon, But Learning Curve Comes First