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Advanced-node semiconductor technology is getting much more complex and challenging, but that isn't slowing things down at TSMC, the world's largest pure-play foundry. At the 2014 TSMC Technology Symposium in San Jose April 22, three TSMC executives revealed rapid progress with company's new 16nm FinFET Plus, 10nm, and 7nm process nodes.
The presenters included Dr. Mark Liu, president and co-chief executive officer; Dr. Jack Sun, vice president of R&D and chief technology officer; and Dr. Cliff Hou, vice president of R&D. Other topics discussed at the day-long symposium included 3D-IC technology, specialty products such as MEMS and high-voltage ICs, and research into new materials to increase mobility and performance. J.K. Wang, vice president of operations, provided an update on manufacturing and capacity.
Underlying the entire event was an emphasis on ecosystem collaboration. "The collaboration we do throughout the supply chain is incredible, and it solves the ever-increasing complexity problems we address," said Rick Cassidy, president of TSMC North America (right), in opening remarks at the symposium. "We are making the impossible possible."
Here are several key takeaways from the advanced-node discussions:
16nm FinFET Processes
The 16FF and 16FF+ technologies are "ready for prime time," according to Sun (left). He noted that the 16FF yield has already caught up with the 20nm planar (20SoC) process node. As a second-generation FinFET technology, he said, 16FF+ can provide an additional 15% die size reduction compared to 20SoC.
Liu said that TSMC plans 15 16FF tapeouts this year, and that compared to 20SoC, 16FF can provide a 40% performance increase at the same power consumption. 16FF+ allows an additional 15% performance increase. Volume production for the 16nm FinFET nodes is expected in 2015. "We are confident that our customers can use this [16nm] technology to produce mobile devices superior to those produced by IDMs," he said.
Hou spoke in detail about TSMC's IP silicon validation for 16FF. He said the company has finished silicon validation for high-speed and high-density standard cell libraries, including more than 8,000 cells. The silicon report shows "very good SPICE to silicon chip correlation." As for memory, TSMC has taped out more than 250 SRAM instances and has finished silicon validation.
Pointing to a 128Mb compiled SRAM instance, Hou said that TSMC can reduce minimum Vcc (supply voltage) by more than 300mV. Peripheral logic can run as low as 0.3 volts, providing further reductions in chip power. TSMC has also completed silicon validation for 1.8V and 3.3V I/Os, analog IP, and eFuse metal.
"All of the silicon reports will be available in two to three weeks," Hou said. "The 16nm FinFET process is very mature and the ecosystem is ready for your design."
And what about 16FF+? Hou said that TSMC was able to improve power, performance, and area in this "second generation" FinFET technology for four reasons:
Combine all these factors, Hou said, and a 16FF+ ring oscillator simulation will show a 20% to 23% speed improvement compared to 16FF. More specifically, standard cells show a 16% to 18% speed improvement, memory shows a 17%-19% speed improvement, eFUSE shows a 13% speed improvement, and I/O devices provide a 3% speed improvement. However, the 16FF+ technology significantly reduces I/O device leakage.
Analog IP, such as PLLs and SerDes, shows a 15% active power reduction. For DDR4 IP, Hou said, TSMC has seen a 20% standby power reduction. All of the design kits and collateral for 16FF+ will be ready by the end of April 2014. Foundation IP will be ready by the end of May, and the complete memory compiler will be available in July, although "for key instances we will support you in May and June," Hou said.
10nm - the Third FinFET Generation
The 10nm node will provide third-generation TSMC FinFET technology. "We have started early engagement with multiple customers for product tapeouts in 2015, and risk production is planned for the end of next year, with a goal to enable customer product launches in 2016," Liu said (right). He noted that the 10nm process can provide a 25% performance increase, a 45% power reduction, and a 2.2X gate density increase over 16FF+. Sun added that 10nm can shrink the SRAM cell size by more than half.
At the outset, Liu said, the 10nm node will use existing immersion lithography equipment. When extreme ultraviolet (EUV) is ready, the 10nm technology will "require a manageable process change to port selected layers from immersion to EUV." Sun addressed the lithography issue by noting that the 10nm and 7nm nodes are both EUV compatible. "There are still a lot of hurdles ahead of us, and we are also exploring multiple e-beam and directed self-assembly as next-generation lithography options," he said.
Sun said that TSMC is making progress with its in-house EUV tool (partnering with ASML) and can print metal one features "nicely." But to support volume production, power output of 125W or 250W is needed. TSMC and ASML have so far demonstrated 30W.
Hou (left) pointed out that 10nm will require double or even "multiple" patterning. As such 10nm will require color assignment during layout, and this will be a "challenge for our current design environment and EDA tools." Another tool requirement is accurate RC extraction, since shrinking BEOL and MEOL dimensions significantly increase metal layer resistance. RC extraction must be color-aware.
The good news, Hou said, is that a color-aware flow "is ready today and has been used to create many test chips to qualify our internal 10nm process design. However, there is still room for improvement, so right now we are working with our partners to improve the efficiency of placement and routing."
Going Even Deeper with 7nm Node
Liu said that TSMC plans to start 7nm risk production by mid-2017, "six months earlier than our every two year cycle." Preliminary design rules will be available later this year. Meanwhile, TSMC has been conducting research into "disruptive" transistor architectures such as those using high-mobility germanium.
"We are in early development of 7nm and we are narrowing down the options," Sun said. Meanwhile, TSMC is researching new patterning techniques that provide dimensions "in range for 5nm logic generation."
For further insights into this information-packed TSMC Symposium, see Brian Fuller's Fuller View blog post, which describes the emerging EDA/IP ecosystem for 16nm and 10nm process nodes.
Richard GoeringRelated Blog Posts
TSMC 2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies
TSMC OIP Forum: 16nm FinFETs, 3D-ICs Gain EDA and IP Support
Photos courtesy of TSMC