Get email delivery of the Cadence blog featured here
Many people talk about the Internet of Things (IoT) and how it will affect our work, health, leisure time, communications, and more. As a recently archived webinar shows, Cadence and ARM have gone beyond mere talk and have developed an integrated design flow for low-power, mixed-signal IoT systems on chip (SoCs) based on the ARM® CortexTM-M0 processor.
The webinar is titled "Addressing MCU Mixed-Signal Design Challenges for SoCs and IoT." It is presented by Diya Soubra, CPU product manager at ARM, and Ian Dennison, solutions senior group director at Cadence. You can access the webinar here. A quick registration is required.
The webinar uses a real IoT example that may appear mundane at first glance - but is very significant to those it will benefit. The example is a wireless pressure sensor monitor that tracks and regulates pressure across pipes in an industrial plant. The sensor communicates by radio to a centralized control unit that will optimize system operation across the whole factory. The design includes analog, digital, and firmware and requires the co-simulation of all three elements.
Why Add a Processor?
Soubra opened the webinar by citing the advantages of adding a digital processor next to an analog block. This practice facilitates data processing, digital filtering, efficiency, auto-initialization, calibration, test, communications, connectivity, and safety monitoring. The ARM Cortex-M0 processor is ideal for an IoT application because it is "accessible," Soubra said. "It is the easiest one to add and the simplest one to design, and it has low-power features and enough performance for such [IoT] applications," he said.
Soubra talked about the power modes available with the ARM Cortex-M0 processor - power off, deep sleep, sleep, and active - and the instructions available to programmers to enable these modes. He described a wakeup interrupt controller (WIC) and the use of state retention power gating.
Soubra also talked about the ARM Cortex-M0 System Design Kit (CMSDK) and showed how it can speed design times. This kit includes a selection of ARM AMBA® AHB and APB infrastructure components; essential peripherals such as GPIO, timers, and UART; example systems; verification IP; and compilation and simulation scripts for Verilog. Software support comes from the ARM Development Suite 5 (DS-5TM) and the Keil MDK-ARMTM Microcontroller Development Kit.
Integrated Design Flow
Ian Dennison presented a Cadence and ARM design flow for embedded ARM Cortex-M processors. That flow is shown below (items in blue boxes come from ARM, while items in red boxes come from Cadence).
To begin, the system specification is captured using the Cadence Virtuoso® Schematic Editor and the Virtuoso Analog Design Environment (ADE). Inputs include a testbench, analog models, low-power intent through the Common Power Format (CPF), and analog/mixed-signal IP. Tools on the ARM side include the CMSDK along with ARM DS-5 and Keil software development tools. The Keil tools are used for firmware design.
System simulation is provided by Virtuoso ADE and Virtuoso AMS Designer tools. Once a verified design is available, RTL and test synthesis for digital blocks can take place in the Virtuoso Digital Implementation (VDI) environment. This environment also includes digital block implementation (place and route). Analog block implementation takes place in the Virtuoso Layout Suite. The final steps are chip integration and signoff.
The rest of the webinar consists of a detailed walk-through of all these steps, using the analog wireless pressure sensor block and a digital controller block as an example. The flow illustrates the importance of creating both a transistor-level model and a behavioral model for analog components. Dennison observed that it took 54 minutes to simulate a DAC (digital-to-analog converter) block at the transistor level compared to 0.4 seconds for the behavioral model. The behavioral model allows analog/digital/firmware co-simulation, but is less accurate than the transistor-level model.
The integrated Cadence/ARM design flow spotlights some new Cadence tools and capabilities. Among these is a new schematic text editor that makes it possible to import RTL from the CMSDK. Another new tool is Schematic Model Generation, or SMG. This allows users to quickly create a behavioral model for an analog component such as a sensor. SMG uses pre-developed, reusable building blocks and also lets users create their own blocks.
Using CMSDK, designers can add bus interface RTL and processor-addressable status and control registers for the sensor block. They can also develop the device driver firmware that allows access to the status and control registers. Designers can then run system simulations within the Virtuoso ADE environment that provide co-simulation of firmware, analog, and digital. The Cadence SimVision product provides extensive debugging support.
Users can also run a low-power, mixed-signal simulation using the Virtuoso AMS Designer. One thing that makes this possible is the ability of AMS Designer to automatically create simulation artifacts from CPF descriptions.
Following floorplanning, analog blocks return to the Virtuoso environment for added details such as process, voltage and temperature variations, and designers build individual blocks using transistor-based design. To help speed things along, Cadence MODGENs can automatically create high-density transistor blocks. Further, the recently announced Cadence electrically aware design (EAD) capability ensures that wires can carry currents without electromigration or IR drop problems.
"Today we presented you with an integration of Cadence and ARM tool chains to address mixed-signal challenges for SoCs for IoT," Dennison concluded. "If you have any SoC for IoT - for factories, hospitals, homes, automobiles, or wearables - the flow will work for you."
Again, to access the webinar please click here.
Related Blog Posts
What Is IoT? What Isn't It?
IoT Focus: IoT Applications Require a New Architectural Vision
Easing Mixed-Signal Design With the ARM Cortex-M0