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When it comes to low-power system design and verification, it's easy to miss the forest for the trees. Focusing at the module level, we may lose sight of the system-level implications of power, according to Maulik Patel, product marketing manager at Cadence and author of a paper at CDNLive! Silicon Valley Oct. 26.
To get some background on the topic, I asked Maulik what he means by "system-level" power verification. "It's when you're running a combination of the full hardware design, in a pre-silicon environment, with the software controlling system power," he said.
Maulik believes there's a looming productivity gap when it comes to power verification. This gap "typically comes from looking at a very narrow scope due to performance and productivity limitations. We get busy looking at the details when performing a given set of tasks. Designers may be focusing on a module so they can do an RTL or gate-level analysis, but they're not looking at how the software can impact power when you're using an end device such as a smart phone." Designers tend to look at systems through microscopic lenses, but they need to start looking through telescopic lenses and then zoom in for a detailed analysis, Maulik said.
Maulik provided an example of a smart phone real-world scenario. A user at a coffee shop realizes that he should be meeting a client. He uses a WiFi connection at the shop for surfing the net, and to locate where he needs to go, he opens GPS applications and finds a route. At the same time he opens an email program and sends a quick email saying that he's on his way.
All these applications are running at the same time. The result could be a peak power surge that lasts for a long time and limits battery life, or causes a failure in the field. This can happen if the real-world scenario is not analyzed and verified to make sure it remains under the allocated power budget. The challenges are compounded with multi-core processors, where different applications are running on different processors and a peak power situation could overwhelm the system.
Power Shutoff Has System Implications
As described in a recent whitepaper, power shutoff (PSO) is a technology that has a considerable impact on system verification. To use PSO effectively, Maulik noted, you need to isolate the block or domain, make sure it's turned on and off in the right sequence, and make sure another design block isn't relying on X states (unknowns) when a block is turned off.
It is important to know what happens with PSO in the context of real-world software applications. That means it's important to simulate, or run, the applications. And that's where emulation comes in. Emulation provides the speed that's needed to run real-world applications, and makes it possible to plug in the actual target hardware. As a further bonus, an automated Dynamic Power Analysis Option is available with the Cadence Palladium line of emulation platforms, including the new Palladium XP.
In short, emulation makes it possible to verify that running a bunch of cell phone apps at once won't cause a vicious power surge. And it can be done long before the hardware is built.
The points mentioned above will be covered in Maulik's paper, which is part of the System Realization track at 3:25 p.m. Oct. 26. The on-line abstract says:
This paper describes an environment and an approach that can enable system-level verification by offering a high-performance verification computing platform together with a methodology to create system scenarios and run them on a prototype of the SoC, to analyze, test, and optimize the design's low power features.
While CDNLive! registration is currently closed, a wait list is available, and technical sessions will be available on a microsite after the conference.