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FinFET transistors represent one of the most exciting new technology developments in recent years, and no wonder - these 3D devices promise huge power and performance advantages at 16nm and below. But the deployment of advanced node designs with FinFETs raises a number of challenges. At the Design Automation Conference (DAC 2013) Tuesday June 4, a panel of experts will discuss these challenges and consider the solutions that are needed.
The discussion will be part of a Cadence-sponsored lunch panel open to all DAC attendees. The lunch and panel will be held 11:30 am - 1:30 pm at the Austin Convention Center in Ballrooms E and F (see Convention Center map here). Panelists will debate issues including process development, tool support, ecosystem dynamics, design challenges, and power/performance tradeoffs. Panelists will represent a spectrum of viewpoints including foundry, IP, EDA, and SoC design.
The panel will be moderated by my former EE Times colleague Brian Fuller, who recently joined Cadence as content director/editor-in-chief. Panelists include:
This informal panel will essentially be a guided conversation about the challenges of getting FinFETs into production. It will be interactive, so bring your toughest questions. But first you need to register. To do so, click here. For a complete listing of Cadence activities at DAC, see our DAC microsite.
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