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Traditionally the first major electronic design conference of the New Year, DesignCon 2015 runs January 27-30 in Santa Clara, California. The conference theme is “where the chip meets the board,” and DesignCon describes itself as “the definitive event for the chip, board, and systems design community.”
The conference is a natural fit for Cadence, which last year identified System Design Enablement as a key part of its mission (see blog posting here). Cadence is now providing tools, IP, services, and software content for end-product development, and has a strong focus on board-level and system-level signal integrity, key topics at DesignCon. Cadence is active in the DesignCon 2015 technical conference and is also exhibiting in the Expo.
Before saying more about Cadence involvement, however, I’ll give a brief general overview of DesignCon, which consists of both a technical conference and an Expo. Produced by United Business Media (UBM), DesignCon is now in its 20th year. Through technical paper sessions, tutorials, industry panels, product demos and exhibits, DesignCon brings engineers the latest developments in PCB design tools, power and signal integrity, jitter and crosstalk, high-speed serial design, test and measurement tools, parallel and memory interface design, semiconductor components, and more.
The technical conference program offers over 100 sessions spanning 14 tracks. Key topics include signal and power integrity, mixed-signal and high-speed serial design, and test and measurement. Keynote speakers include Thomas Lee, professor of electrical engineering, Stanford University (Tuesday Jan. 27); Karen Bartleson, senior director of corporate programs and initiatives, Synopsys (Wednesday, Jan. 28); and Alex Lidow, CEO and co-founder, Efficient Power Conversion Corporation (Thursday, Jan. 29).
Standing room only crowd for signal-integrity presentation at DesignCon 2014
The DesignCon Expo Hall at the Santa Clara Convention Center will bring you the latest products and technologies for signal integrity and high-speed design. You can test and compare emerging tools, discover new vendors, and get free education and training at the Chiphead Theater and vendor sessions. Expo hall hours are 12:30 pm – 6:00 pm Wednesday, Jan. 28 and Thursday, Jan. 29. You can register now for a free Expo pass.
Cadence at DesignCon 2015
In the Expo, Cadence will showcase its Allegro Sigrity solutions for signal and power integrity at booth #515. Demonstrations will include constraint-driven power integrity design and analysis; power-aware memory interface design and analysis of the latest DDR and LPDDR interfaces; multi-gigabit serial link design and analysis; and chip/package/PCB power delivery network co-simulation.
Cadence will participate in the technical sessions as follows:
Date and Time
Wednesday, January 28 2:50pm – 3:30pm Room: Chiphead Theater
Joy Li Solution Flow Architect
ERC and SRC—Advanced PCB Layout Checks for Power-Aware Signal Integrity
Wednesday, January 28 3:45pm – 5:00pm Room: M2
Brad Brim Senior Staff Product Engineer
Panel: System-Level Modeling for IP Enablement
Thursday, January 29 8:30am – 9:10am Room: M2
Phillip Pun Principal Design Engineer
Designing High-Performance Interposers with 3-Port and 6-Port S-Parameters
Friday, January 30 10:40am – 11:20am Room: Ballroom E/F
Taranjit Kukal Product Engineering Architect
A Fast and Accurate Approach to Power Integrity Analysis for Complex SiP
For further information and registration, see the DesignCon web site. For more information about Cadence activities at DesignCon, click here.
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