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The Design and Verification Conference (DVCon), scheduled for 3-6 March 2014, has long been the premier conference for IC verification engineers. This year's conference continues to have a very strong focus on verification, but it is also reaching out to design engineers with increasing content about front-end design.
Stan Krolikoski, distinguished engineer at Cadence and EDA standards veteran, is general chair of DVCon for the second year in a row. "Because DVCon is the descendant of several conferences that emphasized HDLs like VHDL and Verilog, the ‘design' aspect of the conference has often been overshadowed by the ‘verification' side of things," he said. "A concerted effort was made this year to highlight design, especially front-end design, while keeping the strong verification flavor that has caused DVCon's popularity to soar."
To increase the focus on design, two new Technical Program Committee (TPC) vice-chairs—David Black of Doulos and Martin Barnasconi of NXP—have been added. Both are renowned SystemC experts. Further, the TPC has reformed the way it reviews and accepts papers to include more experts from front-end design. "The result is a technical program that meets our goal to turn DVCon into a true design and verification conference," Krolikoski said.
DVCon 2014 has something of interest for almost every design and verification engineer. Highlights include a keynote by Cadence CEO Lip-Bu Tan, a Cadence-sponsored lunch and panel on "System to Silicon Verification," three days of exhibits (Monday-Wednesday), 12 tutorials, 12 technical sessions, and two panel discussions (excluding sponsored lunches). Here is a listing of events at DVCon 2014, followed by a short overview of Cadence activities. For further information about Cadence activities at DVCon 2014, click here.
And don't forget to register! Rates go up after Tuesday, 28 January.
Record-breaking attendance at DVCon 2013 - will another record be set in 2014?
Tutorial 1: UVM - What's Now and What's Next (9:00am - 12:00pm)Tutorial 2: Using UPF for Low Power Design and Verification (9:00am - 12:00pm)
Sponsored Luncheon: The Future of Mixed Signal Verification: From Manual Simulations to Full Regression? (12:30pm - 1:30pm), Synopsys
Tutorial 4: Experience the Next "Wave" of Analog and Digital Signal Processing Using SystemC AMS 2.0 (2:00pm - 5:00pm)
Session 1: System-Level Design - 1 (9:00am -10:30am)Session 2: Formal and Semi-Formal Techniques (9:00am - 10:30am)Session 3: HW/SW Co-Verification (9:00am - 10:30am)Poster Session (10:30am - 12:00pm)
Sponsored Luncheon: System to Silicon Verification - Challenges & Solutions (12:00pm - 1:15pm), Cadence
Lip-Bu Tan Keynote: An Executive View of Trends and Technologies in Electronics (2:00pm - 2:30pm)
Session 4: Advance Methodologies and Testbenches - 1 (3:00pm - 5:00pm)Session 5: Mixed-Signal Design and Verification (3:00pm - 5:00pm)Session 6: Low-Power Design and Verification (3:00pm - 5:00pm)
Panel: Is Software the Missing Piece in Verification? (8:30am - 9:45am) Breker, Intel, Synopsys, Vayavya Labs, Cadence, Mentor Graphics
Session 7: System-Level Design - II (10:00am - 11:30am)Session 8: Advanced Stimulus Generation (10:00am - 11:30am)Session 9: Advance Methodologies and Testbenches - II (10:00am - 11:30am)
Sponsored Luncheon: Accelerating Verification (12:00pm - 1:15pm) Mentor Graphics
Panel: Did We Create the Verification Gap? (1:30pm - 3:00pm)
Session 10: Verification Process and Resource Management (3:30pm - 5:00pm)Session 11: SoC and IP Integration Methods and Tools (3:30pm - 5:00pm)Session 12: Interoperability of Models and/or Tools (3:30pm - 5:00pm)
Tutorial 6: The How To's of Metric Driven Verification to Maximize Verification Productivity (8:30am - 12:00pm)Tutorial 7: Block to System Verification: Smooth Sailing from Simulation to Emulation (8:30am - 12:00pm)Tutorial 8: SoC Verification Challenges Offer Opportunities to Take a New Look at Debug (8:30am - 12:00pm)Tutorial 9: Formally Verifying Security Aspects of SoC Designs (8:30am - 12:00pm)
Sponsored Luncheon: Industry Leaders Verify with Synopsys (12:30pm - 1:45pm)
Tutorial 10: Revolutionary Debug Techniques to Improve Verification (2:00pm - 5:30pm)Tutorial 11: Formal Verification in Practice: Technology, Methods and Applications (2:00pm - 5:30pm)Tutorial 12: Optimizing Coverage-Driven Verification (2:00pm - 5:30pm)
Lip-Bu Tan's Tuesday keynote, titled "An Executive View of Trends and Technologies in Electronics," will look at major trends that are driving the semiconductor industry. Tan will show how time-to-market pressures and the technical challenges of advanced nodes threaten to stifle innovation, and note that software development is becoming the biggest cost in SoC design today. He will show how the electronics industry needs to address these challenges through improvements in design and verification technology.
The Cadence-sponsored Tuesday luncheon is titled "System to Silicon Verification—Challenges and Solutions." Industry experts including EDA visionary and investor James Hogan will present and debate the direction of system verification. Selected users will detail how they've solved some of today's hardest challenges in system and silicon verification.
Frank Schirrmeister of Cadence will participate in the Wednesday morning panel, "Is Software the Missing Piece in Verification?" J.L. Gray of Cadence is organizing the Wednesday afternoon panel, "Did We Create the Verification Gap?"
Cadence speakers will teach Tutorial 6: The How To's of Metric Driven Verification to Maximize Verification Productivity (Thursday morning) and Tutorial #10: Revolutionary Debug Techniques to Improve Verification (Thursday afternoon).
Cadence and/or customers will offer 7 poster presentations and 12 papers during the technical sessions. See the DVCon page on Cadence.com for details. Finally, during exhibition hours, Cadence will be showing its latest verification solutions at booth #505.
For further information and registration, see the DVCon 2014 website.