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DVCon, the premier conference for IC design and verification engineers, runs March 2 to 5, 2015 in San Jose, California. This year’s conference focuses on “hot topics” that are critical to attendees, including system-level design, system-on-chip (SoC) verification and validation, IP reuse, mixed-signal design and verification, and low-power design and verification.
DVCon 2015 includes tutorials, paper presentations, poster sessions, panels, and sponsored lunches. It also hosts exhibits from 5:00 – 7:00pm on Monday, March 2, and 2:30 – 6:00pm on Tuesday and Wednesday. This highly focused, interactive conference provides plenty of opportunities for individual networking and problem solving.
Cadence is heavily involved in DVCon 2015. As listed below, Cadence is holding a sponsored lunch panel Thursday, March 5. Cadence is also participating in 10 paper sessions and has organized two tutorials. An exhibit in booth #505 will display the latest Cadence solutions in SoC and system design and verification.
The highlights below show where you’ll find Cadence during the four-day conference. For a complete DVCon 2015 program, see the DVCon 2015 website.
Note: Tutorials 1, 3, and 4, as well as the lunch, were organized by Adam Sherer of Cadence on behalf of the Accellera Systems Initiative.
Tutorial 1: SystemVerilog Design: User Experience Defines Multi-Tool, Multi-Vendor Language Working Set – 9:00am to 12:00pm
Tutorial 2: Automating Design and Verification of Embedded Systems Using Meta-Modeling and Code Generation Techniques – 9:00am to 12:00pm
Accellera Sponsored Luncheon: What is Needed to Drive Design Efficiency? – 12:00 pm to 1:30pm. Description: A panel of experts will discuss current practices and gaps with a focus on where standards need to go.
Tutorial 3: Next-Generation Design and Verification Today – 2:00pm to 5:00pm
Tutorial 4: SystemC Update and Tutorial– 2:00pm to 5:00pm
Is it possible to take some of the art out of verification, or to provide additional tools that would help engineers master the art? Panelists from Atrenta, Cadence, Intel, Mentor Graphics, and Synopsys will debate that question. This panel is scheduled for Wednesday, March 4, 8:30am – 9:30am.
Join Cadence for lunch on Thursday, March 5, and listen in on a panel on Mastering Verification and Debug Productivity. Industry verification experts will highlight their overall SoC verification and debug challenges, as well as some of the solutions/debug methodologies that they have adopted to improve their overall productivity.
Tutorial 7: Verification 501: Graduate-Level Debug Tutorial – 8:30am to 12:00pm. Description: Last year’s “Revolutionary Debug Techniques to Improve Verification Productivity” tutorial focused on moving beyond printf to use interactive and post-processing techniques to make debugging environments like those built with UVM more efficient. This year’s tutorial will concentrate more on complex RTL, VIP, and SoC-level debugging tasks.
Tutorial 10: Verification Solutions for ARM v7/v8-Based Systems on Chips – 2:00pm to 5:30pm. Description: This tutorial will take a close look at state-of-the-art solutions to address SoC-level challenges and demonstrate a comprehensive flow on how to optimize, verify, and accelerate hardware and software development for ARM-based systems, illustrated through use of case studies.
Session 2: Stimulus Generation—Tuesday, March 3, 9:00am – 10:30am
Session 4: Poster Session—Tuesday, March 3, 10:30am to 12:00pm
Session 5: Testbench Construction—Tuesday, March 3, 3:00pm – 5:00pm
Session 6: Advanced Techniques—Tuesday, March 3, 3:00pm – 5:00pm
Session 7: Multi-Language—Tuesday, March 3, 3:00pm – 5:00pm
Session 10: User Perspectives—Wednesday, March 4, 10:00am – 12:00pm
Session 13: Coverage—Wednesday, March 4, 3:00pm – 4:30pm
For further information about DVCon and registration, see the DVCon 2015 website. Advance registration closes January 27. For further information about Cadence at DVCon, see our microsite.