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If you’re designing an IC today, you have three types of transistors to choose from – traditional bulk planar FETs (down to 20nm), FinFETs (below 20nm), and FD-SOI (fully depleted silicon-on-insulator, 28nm). How can you make the best choice for your design? A session at the recent Electronic Design Process Symposium (EDPS 2015) provided a wealth of information to help you decide.
The three-hour “FD-SOI vs. FinFET” session started with a keynote speech by Tom Dillinger, CAD technology manager at Oracle (right). It then included a panel discussion, moderated by Dillinger, with several industry experts. In this blog post I’ll summarize the keynote speech. For a review of the panel session, see part two of this blog series.
Dillinger’s presentation started with device cross-sections and notable features of each transistor type. He discussed device modeling, parasitic extraction, standard cell library design, and methods for power/performance optimization. The focus was on design tradeoffs. “What makes sense is to evaluate these process options and trade off their pros and cons versus your design requirements,” he said.
Old and New Transistors
The bulk planar transistor has been around for many years. It has, however, been getting increasingly complicated, Dillinger noted. It now has “halo” implants for short-channel punch-through control, implants that offer threshold voltage options (such as HVT, SVT, LVT, ULVT), and implants to provide the lightly doped channel extension. One important point is that the newer transistor types don’t have as many options for threshold voltage as designers had in the past.
The FD-SOI cross-section is different. It includes a thin silicon epitaxial layer over a dielectric, and uses selective epitaxial growth for source/drain contact areas. A channel extension implant is required, but there is no halo implant. FD-SOI has no source/drain diode junction to the bulk substrate. A plus: “You can take the original threshold voltage targets and vary them quite widely by varying the body bias or substrate voltage,” Dillinger said.
For the 28nm node, the uniformity of the FD-SOI thin silicon layer is +/- 5 angstroms over the 300mm wafer, equivalent to a 0.2” variation between Chicago and San Francisco.
Now in its 22nd year, the Electronic Design Process Symposium is an IEEE workshop focused on EDA tools and flows.
In a FinFET transistor, a vertical silicon “fin” is fabricated for the device channel, with a surrounding thin dielectric and metal gate input. Similar to FD-SOI, the FinFET channel region is fully depleted. In the first generation of FinFETs, the fin tops were rounded. R&D efforts are underway to fabricate a more rectangular pin profile.
“The fin is really a very wide, lithographically uniform array of pedestals etched into a silicon substrate,” Dillinger said. “That pedestal now constitutes the transistor channel and the transistor current. It takes a little getting used to.” He noted that FinFETs will likely be fabricated on SOI substrates in the future, but for now all production FinFETs are on bulk substrates.
Tracking Device Parasitics
The different process options have different device parasitics, Dillinger noted. The general FET circuit simulation model consists of a voltage-dependent current source, a parasitic resistance, and voltage-dependent capacitance elements. In the FD-SOI device, there are some differences. First, no junction leakage is present. Secondly, source and drain resistances are increased, due to the thin silicon layer. “Gate resistance is a nasty one,” Dillinger said.
FinFETs have numerous parasitic capacitances due to the topography of the gate traversing over the fin. FinFETs also have a dummy gate at the end of every fin, and these are difficult to extract and model. However, FinFETs have some “great characteristics,” Dillinger said. One is low leakage current due to the electrostatic control of the gate. Another is the high drive current per square micron due to the tight fin pitch.
There are some process options to consider. While bulk planar CMOS libraries offer a number of threshold voltages, it’s not so easy with FD-SOI and FinFETs. However, there are ways to modulate Vt. One is to change the gate length. The best thing, Dillinger said, is to talk to your foundry and ask if you can add a little gate length selectively to some of the transistors in your standard cells.
Device models are also critical. All device types require the development of a compact model, and those are qualified by the Compact Model Coalition, now part of the Silicon Integration Initiative. BSIM models come from the University of California at Berkeley. There are BSIM-CMG models for FinFETs and BSIM-IMG models for FD-SOI. However, Dillinger noted, there are no layout-dependent effect (LDE) parameters currently incorporated into the BSIM-CMG or BSIM-IMG models.
“You’ve got to talk to your foundry about how you’re representing secondary effects,” Dillinger said. “They are not well represented in your CMG models.”
Fins Aren’t Created Equal
Another current limitation is that BSIM models assume each fin is independent and equivalent in behavior. If a single gate is traversing over four fins, the RC parasitic model is approximated using the NFIN multiplier (NFIN=4). “No way are all of these fins exactly the same,” Dillinger commented. “They have some LDE, there are parasitics between them, and you’ve got to extract and reduce a very ugly distributed structure of Rs and Cs.”
The FinFET 3D geometry introduces new sources of variation, including:
When it comes to library development, Dillinger said, the most important thing to consider is your power/performance optimization strategy. Synthesis tools, he noted, may be looking for multiple Vt libraries. If you’re planning to use an FD-SOI back biasing technique, “making sure you’re in sync with your logic synthesis flows is very important.”
“What I can’t stress enough is that you need to talk to your foundry,” Dillinger concluded. “Talk about parasitic extraction and how you’re going to annotate those parasitics. Talk about how they can help you consolidate those parasitics, so you can annotate them to a SPICE model and get a true, parasitic-driven circuit simulation analysis.”
Related Blog Posts
EDPS 2015: Choosing FinFET, FD-SOI, or Bulk Planar FETs (Part 2)
EDPS 2014 Workshop – a Review of FinFET Parasitic Extraction Challenges
Webinar Review: How FinFET Processes Will Change Analog IC Design
DAC 2014 Panel: FinFET IC Design Poses no Roadblocks, but Lots of Details