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If you're involved - or just interested - in any aspect of low-power electronics design, you'll find a lot of good information at a one-day Low-Power Technology Summit at Cadence headquarters in San Jose, California October 18. Highlighting the event is a keynote by Jan Rabaey, professor of electrical engineering and computer science at the University of California at Berkeley, and somewhat of a "rock star" when it comes to low-power electronics and EDA.
With a full day of speakers from Cadence, Cadence partners, and customers -- and a closing panel -- the summit will bring you up to date on the latest low-power design methodologies. The summit covers verification, physical implementation, and signoff. Several other notable items on the agenda include:
Here's the agenda as of Sept. 24:
So, who is Jan Rabaey? For starters, he's been at the EECS faculty at U.C. Berkeley since 1987, where he currently holds the Donald O. Pederson Distinguished Professorship. He is the scientific co-director of the Berkeley Wireless Research Center (BWRC) as well as director of the Multiscale Systems Research Center (MuSyC). He has authored a wide range of papers in signal processing and design automation. You can read more here.
Rabaey literally "wrote the book" on low power design. It is called Low Power Design Essentials and it is available from Amazon. For a detailed review of a one-evening "short course" on low-power design that Rabaey gave earlier this year, see Steve Leibson's blog post on Low-PowerDesign.com.
The Low-Power Technology Summit is free but you need to register, and space is going fast. You can sign up here.