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Physical synthesis with Cadence Encounter RTL Compiler Advanced Physical Option can greatly reduce power and area while improving frequency – but you need to follow the right methodology for the best results. That’s the message that Ravi Vaidyanathan, design implementation and integration lead for wireless platforms at Freescale, brought to the Front-End Design Summit held at Cadence San Jose headquarters December 11, 2014. A video replay of this talk is now available to Cadence Community members.
While noting the advantages of physical synthesis, Vaidyanathan passed along a warning -- don’t “over margin” by adding too much uncertainty to timing paths. He noted that many designers tend to over-margin by 10 to 20 percent. “I think you are actually worsening the problem by trying to over-constrain every path in the design,” he said. “The area goes up and it becomes a big problem.”
Freescale’s Ravi Vaidyanathan speaks on “do’s and don’ts” of physical synthesis at the Cadence Front-End Design Summit
Vaidyanathan related how Freescale used Encounter RTL Compiler Advanced Physical with the second version of a vector signal processing acceleration (VSPA) core. Before the Encounter tool, he said, “we struggled a lot with the disconnect between place and route and synthesis.” With the tool, “Cadence has really brought multiple technologies into the synthesis tools that helped us close timing between place and route and synthesis.”
Getting Physically Aware
One important technology in Encounter RTL Compiler Advanced Physical, Vaidyanathan said, is physically aware mapping. Here, the tool uses the Encounter Digital Implementation System engine natively to run technology mapping and structural optimization on critical paths. “The idea is to bring physical information into your optimization much earlier, so it can influence better timing closure and logic depth and do a great job of choosing the appropriate cells in a physical path,” he said.
Another important Encounter RTL Compiler Advanced Physical technology is physically aware structuring, which optimizes high-congestion structures such as those created by mux logic. This is especially important for VSPA cores, which have multiple levels of mux logic. The Encounter tool also adds two cost functions for optimization – utilization and congestion. These cost functions are “really important to getting a better critical path optimization,” Vaidyanathan said.
The proof is in the numbers, and Vaidyanathan showed comparative results on a VSPA block without the tool and with the tool. The block had around 1.4M instances. Without the tool, vertical congestion was 2.54%, worst negative slack was 36 ps, and there were 8,385 failing paths. With the tool, vertical congestion was 0.28%, worst negative slack was 0 ps, and there were no failing paths. Encounter RTL Compiler Advanced Physical runtime was 44.7 hours.
The Right Methodology
With a sophisticated EDA tool like Encounter RTL Compiler Advanced Physical, methodology really matters. Vaidyanathan gave the following advice as he discussed the tool flow:
Basically, the Encounter Digital Implementation System pre-clock tree synthesis (CTS) environment must be duplicated in the Encounter RTL Compiler Advanced Physical flow. The presentation notes how this can be done. The output of the compiler tool is a placed Encounter database.
As noted earlier, Vaidyanathan warned that over-margining will decrease quality of results and increase runtimes for Encounter RTL Compiler Advanced Physical. Also, he noted, “in RCP you don’t want to over-margin because you are actually running place and route as a part of synthesis, so you want to run at the target frequency.”
Both a slide presentation and video are available for Vaidyanathan’s talk, in addition to other Front-End Design Summit presentations. A Cadence Community log-in is required – quick and easy registration if you don’t have one.
Related Blog Posts
Front-End Summit: Avoiding Routing Congestion with High-Level Synthesis
Front-End EDA Panel: “Empowering” the RTL Designer
Technology Summit: Deep Insights into Synthesis, Verification, and Test