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The design and manufacturing challenges of 20nm ICs are formidable, and will not be solved by loose collections of point tools. At the recent Global Technology Conference (GTC), Cadence presented its view of 20nm challenges and previewed a comprehensive 20nm design methodology that encompasses custom design, digital design, and signoff.
The presentation was offered by Wei Lii Tan, senior product marketing manager for digital implementation at Cadence. Tan began by noting that the overall Cadence 20nm solution will be part of the EDA360 vision, and will include activity at the System Realization and SoC Realization levels, as well as the Silicon Realization methodology discussed in his presentation. (A recent Cadence whitepaper, previewed here, says more about how the Silicon Realization concepts of unified intent, abstraction and convergence play into a unified 20nm solution).
So why are companies in areas such as mobile computing, servers, smartphones, and wireless communications looking to migrate to 20nm? "The benefit of 20nm, first of all, is differentiation - from a power perspective, from a performance perspective, from an area perspective," Tan said. Advantages of moving to 20nm, he noted, can include 30-50% better performance, 50% area reduction, and around 30% switching power savings.
But 20nm comes with some technology challenges, including:
In particular, there is much concern about double patterning, which is necessary to accurately print images when wire pitches are below 80nm. "A combination of advanced design rules and double patterning is required to achieve the best possible pitch," Tan said. (For a further explanation of why double patterning is needed at 20nm, see Steve Leibson's latest GTC blog post.)
Cadence, Tan noted, has been making a significant R&D investment in 20nm since 2009, has completed multiple 20nm tapeouts, and is actively collaborating with foundry and IP partners. The Cadence 20nm methodology includes cell and IP design and simulation through the Virtuoso custom IC design system; synthesis with RTL Compiler; design exploration, planning, and implementation with the Encounter Digital Implementation system; and physical verification and manufacturing signoff.
More specifically, the Cadence 20nm design implementation flow includes the following steps:
Why double patterning-aware placement and routing? Double patterning requires the successful decomposition of the design layout into multiple masks, and that this places some restrictions on the layout. Placement tools must understand that certain cells cannot be placed next to one another. Routing tools must model the way a layer will be separated into two layers, or "colors," that can be recombined in lithography. This is all explained further in the 20nm whitepaper mentioned above.
20nm double patterning-aware placement
The Cadence flow supports both "in design" and standalone physical verification for double patterning at 20nm. Physical implementation includes built-in DRC engines and a correct-by-construction double patterning approach. Physical signoff, integrated into the design environment, assures that colorization and decomposition are handled correctly.
In conclusion, Tan noted, Cadence is building a comprehensive methodology all the way from standard cell development to physical implementation and manufacturing, and is actively working with customers and foundry and IP partners to make sure the tools are ready for early adopters. From my perspective, the key word in all this is "comprehensive." You can't assure 20nm success any other way.
Other Industry Insights posts about the GTC conference:
GTC Panel: Getting Best Use from Older IC Process Nodes
GTC Panel: CEOs Navigate a Changing IC Ecosystem
GTC: GLOBALFOUNDRIES Charts Course for 28nm, 20nm and Beyond