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Development work is underway on the 10nm process node - but can we get there with conventional lithography? In a recorded presentation available at the Cadence web site, Lars Liebmann, distinguished engineer at IBM, says yes - but he notes that it will take a great deal of collaboration between foundries, EDA providers, and semiconductor IP suppliers.
Liebmann was a speaker at the Cadence DAC Theater at the Design Automation Conference (DAC 2014) in June, where over 40 speakers - mostly customers and partners -- offered informal half-hour presentations. Audio recordings and slides are now available for most of those presentations, including Liebmann's presentation, at the Cadence DAC microsite.
Liebmann's paper was titled "Overcoming pattern-induced place-and-route challenges at 10nm." The paper lists two IBM authors (including Liebmann), one ARM author, and four Cadence authors. Topics include double patterning, odd cycle prevention, color-aware placement, via pitch and location, and the sidewall image transfer (SIT) methodology for multiple patterning.
Playing Tricks With Light
A decade ago, few would have predicted that we'd be manufacturing chips at the 10nm process node using equipment based on 193nm wavelengths, but with continuing delays in extreme ultraviolet (EUV) lithography, that's where we are heading now. "It's a very exciting time for lithography," Liebmann said. "We're pulling all sorts of tricks out of a hat to keep going, even though we really ran out of resolution 10 years ago."
One of those "tricks" is double patterning, which has become essential below 22nm. Double patterning uses extra masks to resolve layout features that cannot be reliably printed following a single exposure. To indicate which feature goes onto which mask, layouts are colored and nearest neighbor features must have opposite colors.
Since double pattering becomes necessary at 14nm, 10nm can be regarded as the second generation of double patterning. One difference compared to 14nm is that 10nm packs more interacting layout features into smaller spaces. As a result, Liebmann noted, there are more opportunities to create odd cycles, which happen when three features are interacting in a small space and they have only two colors to separate them. Bringing in a third color and doing triple patterning may be the only way to resolve an odd cycle.
At 10nm, Liebmann noted, there's a need for color-aware placement to resolve cell-to-cell color conflicts. "This is an interesting new challenge for the EDA community," he said. There are three potential ways to resolve cell-to-cell conflicts:
Liebmann's presentation also noted that the potential for via odd cycles accelerates in 10nm, and that explicit odd cycle prevention is needed in routing. "The number of vias where you have to worry about color conflict is increasing tremendously," Liebmann said. Pin access in routing is limited not just by wire congestion, but also by via color conflicts. The router needs to actively prevent pin access that causes via odd cycles.
Double Patterning Gets Complicated
At 14nm double patterning is fairly simple. It uses a technique called litho-etch litho-etch (LELE), which basically places half the features on one mask and half on another. Then both masks are exposed to build the layout features on the IC.
However, LELE can only resolve a minimum pitch of 50nm. At the 10nm process node we really need to get down to 40nm, Liebmann said, and the way to do that is through a process called sidewall image transfer (SIT) or self-aligned double patterning (SADP). This is a complicated process in which the foundry inserts shapes called "mandrels," deposits sidewalls around the mandrels, does a lot of processing, fills in dielectric, and removes dummy features. This process is much more challenging than LELE, and results in more complex design rules.
The SIT methodology uses a block mask (sometimes called a cut mask) to removed unwanted features. A number of requirements are specific to block masks. For example, Liebmann showed that the block mask requires tip-to-tip line end rules. Moreover, an optical proximity correction (OPC) tool will tend to over-compensate and insert metal shapes where you don't want them.
The solution, Liebmann said, is to restrict the layout space that the block mask has to handle. "This is not something you can do when the design is done," he said. "It has to be actively managed inside the router to make sure the line ends are positioned so you can create a block mask that is relatively simple."
Making it Real
Liebmann's presentation was not just theoretical - it was based on collaboration between IBM, ARM, and Cadence. Engineers used a cell from an ARM prototype library to run tests using Cadence Encounter Digital Implementation System placement and routing software. "It's been a lengthy development effort and we've had nothing but support from the Cadence team," Liebmann said. As a result, he observed, there's a solution in place that has color-aware placement, explicit via coloring, odd-cycle avoidance in routing, and fill wire generation.
"10nm is the most complicated node yet, but the design infrastructure is on track for product implementation," Liebmann concluded. "The important message is that we really need to engage with our infrastructure partners early."
To hear this presentation and view the slides, click here and scroll down to Tuesday, June 3, 11:00 am. No registration is required.
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