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NAND Flash and DRAM have had a great run through many process generations, but the good times for these architectures may be coming to an end, according to a keynote speaker at the Flash Memory Summit Aug. 21, 2012. Sung Wook Park, executive vice president for R&D and SK Hynix, talked about the scaling limits of conventional memory and discussed three new alternatives - PCRAM, STT-RAM, and ReRAM.

The Flash Memory Summit runs Aug. 21-23 in Santa Clara, California. The conference includes nine keynote speeches and a number of technical presentations, and some of the presentation materials, including slides from the Park keynote, are already on-line here. Cadence is a platinum sponsor of this year's conference.

"Everybody knows that conventional memory is about to hit scaling limits," Park said. "We continue to find ways to push the technology another couple of process nodes. In addition to this progress, a number of different types of memory have been introduced."

Hitting the Scaling Wall

Park noted that DRAM costs per Gbit have been decreasing by an average of 33% annually since 1991, but questioned whether this can continue beyond 2ynm processes.  He talked about the difficulty of manufacturing DRAM capacitors as process nodes decrease. He also noted that NAND process scaling has increased bit density/area by 50% per year, and questioned whether this trend can continue as well.

3D NAND structures could help with the scaling problem, Park suggested. He briefly reviewed several proposed 3D NAND structures including the Toshiba p-BiCS, Samsung TCAT, Hynix 3D FG, and Micron architectures. He cited low yields and poor data retention as potential problems for 3D NAND, and said more research is needed to improve cell optimization. (3D NAND was also a topic at last year's Flash Memory Summit, as noted in this blog report).

So why is there a need for new memory technology? DRAM is running into problems with cell capacitance below 2xnm, and high densities (over 8 Gbits) are challenging, Park said. NAND Flash FG (floating gates) have so few electrons below 1xnm that losing even 10 electrons could be a serious problem. Data retention and reliability degradation are growing concerns.

What's needed, Park said, is new memory technology that can replace existing DRAM and NAND, upgrade system performance, and provide a more scalable solution. It must be drop-in compatible with existing memory and have favorable cost, power, reliability, and performance characteristics.  Here is what he had to say about opportunities and challenges for three new technologies.

PCRAM - Phase-Change RAM

Advantages: Most mature of the new technologies presented, non-volatile, good scalability, "a promising solution that combines the advantages of DRAM and NAND Flash." Hynix has successfully manufactured a 42nm 1Gbit PCRAM and a 2xnm device is in development.

Concerns: Cost for DRAM-like applications. Relatively large reset current required.

STT-RAM - Spin Transfer Torque RAM

Advantages: Magnetic Tunnel Junction (MJT) allows non-volatility, high speed operation, good scalability. Device performance similar to DRAM, making it a potential DRAM replacement.

Concerns: Cost competiveness with DRAM, active power, bandwidth. MJT stacking structure is complicated. "MJT material is very fragile and can be damaged during etching and post-processing."

ReRAM - Resistive RAM

Advantages: Memristor cell has very simple materials and structure, and low power operation. High-density storage capability makes it a potential NAND or hard drive replacement. "Excellent performance and endurance - a candidate for high-performance storage devices."

Concerns: Switching mechanism still unclear. "Producing ReRAM is still a ways away. We need a better understanding of stability and switching mechanisms."

Hynix is working on all three memory types, Park said. At this time the company views PCRAM as a candidate for working memory, STT-RAM for working or cache memory, and Re RAM for storage. Slides for Park's Flash Memory Summit keynote provide a lot more detail and are available here. For a summary of Cadence events at the conference, click here.

Richard Goering