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Cadence offers extremely broad low-power technology that impacts many tools and flows for IC and systems design, according to Paul Cunningham (right), vice-president of R&D for front-end design at Cadence. At the recent Low-Power Technology Summit, Cunningham showed what differentiates Cadence low-power technology in such areas as physical implementation, front-end design, test, analog/mixed-signal, signoff, and semiconductor IP.
“We are passionate about power and we want to continue making it a number one priority for our company,” Cunningham said. It is this passion that led to the Low-Power Technology Summit, a one-day event in November at Cadence's San Jose headquarters. Slides and videos are now available for many of the presentations, including Cunningham’s speech. (A Cadence log-in is required, with quick and easy registration if you don’t have one.)
Cunningham, co-founder and CEO of Azuro before its 2011 acquisition by Cadence, talked a bit about his own passion for low power first. He did his PhD research in asynchronous circuits, which are inherently low power because every function takes as long as it needs. He then started Azuro, the creator of clock concurrent optimization, a technology that brings some of the low-power benefits of asynchronous design into the synchronous world.
At Cadence, Cunningham started working in product engineering for place and route products. Here he realized that the key customer concern was “power, power, power in all its shapes and sizes.” He then moved to front-end design. This, he said, “opened my eyes further” into the pervasiveness of power consumption across every part of the IC design cycle.
Ten years ago, Cunningham said, there was an “elephant in the room” because there was no methodology and no ecosystem for designing multi-voltage, power shutoff ICs. Cadence pioneered a low-power intent format—Common Power Format (CPF)—and adapted its tools to support it. Today an effort is underway to derive a common intent format with IEEE 1801 or Unified Power Format (UPF). The intent format is not the big elephant in the room any longer, Cunningham said, but the journey is far from over yet.
While Cadence has passion for low-power design, “we’ve got to channel that passion into something we can execute on quickly,” Cunningham said. As such, Cadence is looking at what makes sense for vertical markets such as mobile computing, network and cloud, automotive, and Internet of Things. “We should be focused on things that deliver the best power ROI for different targeted markets,” he said.
Cunningham identified some “key Cadence differentiators” in low-power design, as follows:
The Palladium acceleration/emulation system makes it possible to run massive amounts of simulation very quickly. You can profile the power performance and apply techniques such as dynamic voltage and frequency scaling (DVFS) as needed. You can also run a very fast prototype synthesis, and use that prototype to identify peak power windows. The diagram below shows how.
Voltus is a power integrity signoff tool with a massively parallel architecture that can handle SoCs with 400 million instances in 21 hours. Voltus is also integrated with Cadence Sigrity tools for package and board-level power and signal integrity. Users can take package models out of Sigrity and move them into Voltus.
Complexity is so high in low-power ICs that a traditional dynamic simulation is not enough. Conformal Low Power can run static checks on the design and the power intent file.
CLP can also be used for transistor-level low power verification. You can take a gate-level netlist and power intent, and abstract the domain boundary netlist and generate SPICE cell views. This provides a transistor-level model of the power domain interfaces.
The custom/analog Virtuoso Schematic Editor can work with CLP in a mixed-signal low-power verification mode as shown below.
Cadence not only provides design tools for low power—the company also provides design content in the form of semiconductor IP. Cunningham observed that Tensilica Xtensa IP can “scale to lower voltages than anything in the market.” Here are some features of other Cadence IP:
“Power consumption in test is increasingly problematic,” Cunningham said. “We are also making sure that we can test complex multi-voltage, power shutoff designs.” Cadence provides a Power Test Access Module for controlling power domains during test. Cadence Design for Test (DFT) software can fill in “intelligent” don’t care values, leverage clock gating during capture, and use timing-driven Q-gating in synthesis.
Cunningham concluded by emphasizing that “we are fully behind alignment with IEEE 1801. We have a great CPF-based solution, and we will continue to invest in that, but we’ll do what we can to ensure the industry can align on a common format and interoperate.”
Again, you can watch the entire 45-minute video presentation online, as well as other presentations from the Low-Power Technology Summit.
- Panel: Engineers Debate Progress of Low-Power Design
- Q&A: Former Azuro CEO Explains Clock Concurrent Optimization
- Why Cadence Bought Azuro—a Closer Look