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A major advancement in 3D-IC through-silicon via (TSV) design will be unveiled Tuesday (Dec. 13) as representatives of CEA-LETI and ST-Ericsson describe the development of a three-die stack with wide I/O memory and logic. This tapeout is the result of a collaboration between these two organizations and Cadence, which provided the design tools and the wide I/O controller IP for the project.
The project will be described in a paper presented by Pascal Vivet, research engineer at the CEA-LETI research institute, and Vincent Guerin, senior digital design engineer at ST-Ericsson, at the RTI 3-D Architectures for Semiconductor Integration and Packaging conference in Burlingame, California. This proof-of-concept design is a step forward in several respects:
The project actually involved three test chips - memory plus logic, two SoCs stacked together, and memory stacked on top of two SoCs. Here's a diagram of the three-die stack. The package is a 12x12 BGA with 581 balls. It includes several thousand micro-bumps and around 2,000 TSVs per SoC. The diagram shows the face-down orientations of the three dies.
Expertise in Three Dimensions
The LETI research institute brought its manufacturing expertise to the project. LETI offers TSV "toolboxes" including via-first, via-middle, and via-last methodologies (via middle was used on the SoCs in this project). LETI has a 300mm 3D manufacturing line and has experience in stacked die implementations.
ST-Ericsson designed the WIOMING SoCs used for this project. These chips include an ARM host CPU, DSP and ASIP engines, and multi-core CPU backplane. ST-Ericsson also developed the 3D asynchronous NoC. (Conceptually, a NoC replaces a fixed bus with a packet-based approach and a layered methodology. NoC implementations have primarily been used with 2D multi-core SoCs).
The thing that's different about this NoC is that it works in three dimensions. Employing fast serial data links and fully asynchronous logic, it achieves 550M transfers/second throughput in the 2D (intra-die) direction, and 200M transfers/second in the 3D (inter-die) direction. Serialization reduces the number of TSVs at the 3D NoC interface. The NoC also provides fault tolerance and supports a design for test (DFT) architecture based on test wrappers.
Wide I/O memory is a new DRAM technology and an emerging JEDEC standard that calls for a 512-bit wide interface and 12.8GB/second bandwidth. In addition to high bandwidth, it promises 2X the power efficiency of LPDDR2 and LPDDR3. Beyond the 12.8 GB/second bandwidth in the initial JEDEC spec, increasing DRAM frequency to 266 MHz and using dual data rate transfers will eventually provide more than 34 GB/second.
The 3D-IC project used the Cadence wide I/O memory controller, introduced in March 2011. This controller IP is fully compliant with the JEDEC wide I/O specification and includes advanced low-power features and memory built-in self test (BIST) tests. Cadence also provides a PHY, verification IP, and memory models.
The 3D-IC project used the Cadence Encounter Digital Implementation System 3D-IC flow, including Encounter Power System, Encounter Timing System, floorplanning, routing, and extraction and analysis. The overall flow was introduced in early 2011 and is described here. The flow makes it possible to automatically create and assign TSVs; floorplan with a knowledge of what's on adjacent dies; perform TSV routing; extract TSVs; and run IR drop analysis on 3D stacks.
The overall message is that wide I/O 3D-IC technology is ready for production, and that heterogeneous die stacks with more than two dies have arrived. The result will be a new generation of low-power, high-performance mobile devices - and given the competitive consumer market, they won't be long in coming.
For a more detailed view of this development, see Steve Leibson's blog post.