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Albert Chen, field applications and marketing manager at Faraday Technology, has good news and bad news about low-power IC design. The good news -- low-power design implementation has become much more efficient in the past few years. The bad news -- 60 percent of potential power savings remains untapped.
Chen participated in a low-power panel at the Cadence Ecosystem booth at the recent Design Automation Conference, and he also gave a half-hour presentation at the booth. In an interview following the panel, he offered some further comments about Faraday’s experience with low power design. And this experience is, in fact, extensive. Faraday, a silicon IP and fabless ASIC design provider, completes some 300 tapeouts per year.
A bit of background is needed before delving further into the interview. In his presentation, Chen talked about a mobile digital TV demodulator chip that Faraday designed in 2006, and a multimedia processor ASIC that Faraday designed in 2008. Both used power management techniques. While the 2008 chip was 3X more complex than the 2006 chip, it was designed in 45 percent of the time.
What caused this leap in productivity? That’s the first question I put to Chen in our interview, and his answer is in the short video clip below.
As Chen suggests in the above video clip, Faraday’s adoption of the Common Power Format (CPF) and platform-based approach are key to delivering good power results for its ASIC design customers. With the platform-based approach, the company starts with a “generic” solution that supplies 80 percent of what customers want, and treats silicon IP as customizable plug-and-play blocks to get the remaining 20 percent. Chen said that Faraday’s platform SoCs support a number of low-power design techniques, including dynamic and adaptive voltage and frequency scaling. Faraday also provides an operating system and drivers to run the SoC.
While progress in low-power design is impressive, something is still missing. In his presentation, Chen noted that current techniques address less than 40 percent of the potential power savings. The remaining 60 percent are at the systems level. Here’s what Chen had to say about how we can address it:
What advice would Chen give to ASIC design teams that are new to low-power design?
“Don’t be afraid – that’s the key. A lot of Faraday customers are first-time ASIC customers. There is some hand-holding, but I think the ASIC environment and flows are mature enough that we have lowered the barriers dramatically over the past four or five years. It can be done. It’s a great time to build chips right now.”