Webinar Review: How FinFET Processes Will Change Analog IC Design

2 Apr 2015

Webinar Review: How FinFET Processes Will Change Analog IC Design

Industry “wisdom” once held that analog/mixed-signal designers will stay away from leading-edge process nodes that employ FinFET transistors, but that turned out to be wrong. FinFET processes in fact bring many advantages to analog/mixed-signal designers, but they’ll have to accept a number of changes in the way IC design is done, according to Eric Naviasky (right), fellow in the IP Group at Cadence.

In a recently archived webinar hosted by Design World magazine, Naviasky went into considerable detail about the advantages of FinFET processes, the drawbacks, and the new design techniques that they require. Most commercial foundries use FinFETs at process nodes such as 16nm, 14nm, and 10nm. As Naviasky noted, many of the design changes have more to do with the small size of the devices than the FinFET 3D architecture itself.

On the plus side, Naviasky said, the analog behavior of FinFETs is very nice, performance is great, and digital control is practically free. But matching, layout, and simulation speed pose challenges. Many companies are in production with FinFET processes and the yields are good. His overall assessment: “Come on in, the water is fine.”

A Big Change for Analog

FinFETs are “one of the neatest things that has happened to analog design in quite a while,” Naviasky said. He added that the shift to FinFETs is comparable in magnitude to earlier changes to silicon transistors, bipolar devices, and CMOS. “Because the size and nature of these [FinFET] devices is substantially different, we all need to learn new tricks,” he said.

Naviasky cited the following benefits of FinFET processes, compared to previous nodes:

G_ds (output conductance) is much lower and output impedance is higher. “That means it is possible to get decent gain out of a single stage.”
Subthreshold slope is close to ideal.
G_bs (body effect) is much smaller.
G_m (transconductance) is high. Devices that have high F_t, high G_m, and very low gate capacitance are potentially very fast devices.
Device parasitic capacitances are small.
Most FinFET processes have a nice selection of voltage thresholds.

Another benefit is that “digital is essentially free on these [FinFET] processes. Digital gates are so small that there’s not much area penalty for using them.” This makes it easier to use digital control. “Yesterday’s auto zero has been replaced with today’s convolutions and DFTs,” Naviasky noted.

Challenges of FinFET Processes

Nothing comes for free, and Naviasky pointed to several areas of challenge posed by FinFET processes. One is current density. He noted that drain saturation current of devices is very high, much higher than the “skinny metal” that hooks up the devices is going to be able to carry. “That’s perhaps the biggest challenge that these processes are bringing along,” Naviasky said.

Another challenge is that tiny devices have poor absolute matching. A third challenge is metal resistance—because you scale everything at an advanced process node, metal is thin, narrow, and resistive. There are thicker metals at the top of the stack, but these levels are typically reserved for power distribution.

From a design point of view, analog/mixed-signal designers will encounter the following:

Fins only come in one width
Transistor length is heavily restricted
Designers will have to change how they construct bias blocks and high-gain stages
Sizing characteristics come with a new set of rules
Sizing for noise is no longer practical
Device models are complex and take a long time to simulate
Parasitic capacitances dominate the design. Schematics without good capacitance estimates mean very little; only those with extracted Rs and Cs count

Layout can be “very painful” because of density and regularity rules, Naviasky said. To begin, all devices have to be on a grid. You cannot mix different sizes and types of components without buffer zones. Density rules are very strict. Resistors come in only a few sizes, perhaps only one. “Attempting to port from an older node and just copying your design rules does not work,” Naviasky said.

There are, however, workarounds for most of these problems. For matching, you can use stacks of devices or use digital correction. To speed simulation, you can use brute force (bigger servers, parallel execution) or use behavioral modeling. Dynamic circuits can help you get around electromigration current limitations.

Naviasky said that layout designers need to use templates, and that this is “probably the only way layout is going to work now.” With templates, he said, you lay out blocks that have uniform densities on all the critical layers. This is not to protect the individual blocks, it is to protect the neighboring blocks.

Naviasky also suggested that layout designers should group all devices of a type into a single area and accept the higher interconnect distance. Also, it’s important to floorplan very early to help with parasitic resistance and capacitance estimation.

You can access the webinar by clicking here. Design World will request a short registration.

Richard Goering

Industry Insights Blogs