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What a whirlwind of two months it has been! And it has been totally worth it, with CDNLive India featuring a huge number of customers, fantastic user-authored presentations and insightful keynotes.
A more detailed review will follow, but here is the list of Best Paper Award winners that were declared in the nine tracks:
Digital Implementation Track
Importance of Custom Clock Structure For High Frequency CPUs - Samsung
Digital Front-End Design Track
This was a tie between:
1. Achieving Faster Turnaround-Time for Formal Verification for Multi-Million Gates Design - Intel
2. Novel Methods for Logic BIST Test Time Reduction and Testability Improvement in Safety-Critical SoCs - Texas Instruments
Digital Full Flow & Signoff Track
An Insightful Journey of 7nm ASIC Tapeout Using Innovus-Tempus Solutions - eInfochips
Custom/Analog Design: Verification Track
Improved Post-Layout Simulation and Probing Methodology with Revamped Stimuli - Intel
Custom/Analog Design: Implementation Track
Managing Electrical Reliability During Layout Implementation - STMicroelectronics
System Verification: Advanced Verification Methodology Track
PSS Coverage at SoC Level Using Perspec – Qualcomm
IP/Subsystem Verification: Performance and Smart Bug Hunting Track
Efficient Methodology for Design Verification Closure for Complex SOCs using Save & Restore – Samsung
System Verification: Emulation and Prototyping Track
Shortening Design and Firmware Validation Timelines Through Reuse of UVM Simulation Testbench on Hardware - Samsung
PCB Design & System Analysis Track
Improve Productivity With Cadence Allegro Symphony Team Design - L&T Technology Services
Congratulations to all the winners!