DVCON India 2021 - A Quick Summary

Another DVCon India, the ‘Mecca’ for Design and Verification Engineers, took place from December 14-16, 2021. The theme of this virtual event was on the convergence of AI, 5G and edge computing. DVCon India always provides a superior learning experience and this year was no different, with keynote sessions, panel discussions, tutorials, papers, and poster presentations on challenges and breakthroughs in design, verification, and validation.

Cadence was proud sponsor of two tutorials and a panel discussion at DVCon India 2021.

Here is a quick summary and some key takeaways from the event. 

Cadence Sponsored Panel: "Today’s SoC Verification Challenges and Solutions"

Cadence organized a panel discussion on Day 2. The panelists included Nirmal Arumugam, Principal Engineer, Qualcomm, Pankaj Kakkar, Senior Engineering Manager, Cadence, and Sukumar S. Raghuram, Senior Principal Engineer, Intel.  The panel was moderated by Nick Heaton, Distinguished Engineer and SoC Verification Architect, Cadence. In this lively discussion, panelists discussed:

• More innovations in architecture are needed to meet the current demands and to address Moore’s scaling
• Debugging of complex systems is becoming more challenging as the systems are getting bigger
• New technologies like Universal Verification Methodology (UVM) and Portable Stimulus Standard (PSS) are the saviors
• Importance of Simulation/Emulation and FPGA prototyping.
• Usage and integration of Machine Learning-enabled tools to make debugging smarter and reduce time-to-market

Cadence Sponsored Tutorial 1: “Benefits of a Common Methodology for Emulation and Prototyping”

This tutorial was presented by Michael Young and Juergen Jaeger from Cadence. They shared the benefits of emulation and prototyping, especially in complex designs, to accelerate the verification process and meet challenging schedules.

Michael spoke about Cadence’s emulation and prototyping systems that comprise of a “Dynamic Duo” of two tightly integrated systems: Cadence Palladium Emulation Platform, which is optimized for rapid predictable hardware debug, and Cadence Protium Prototyping platform that is optimized for the highest performance for pre-silicon software validation.

Emulation and prototyping are sometimes considered expensive, but they really pay for themselves accelerating time to market and helping in increasing the quality and revenue as well. While Palladium has cost strength in SoC hardware chip verification from fast buildup to fast market leading productivity, Protium on the other hand with its superior performance makes pre-silicon bring-up and software/Hardware integration complete faster.

When the RTL is stable, it makes sense to use FPGA-based prototyping like Protium X1, which makes it easy to complete the design. So, using a combination of both enables to stay to schedule of the project and even accelerates.

The implementation and debug software from Cadence ensure the prototype has all the debug and interface capabilities to start the firmware and software development at the earliest and is reliable. The effectiveness of Protium usage in the figure shows a comparison with traditional schemes for prototyping

Cadence Sponsored Tutorial 2: “Achieve Faster Regression Throughput by Applying Machine Learning and Advanced Technologies”

The second tutorial by Cadence was presented by Ankur Jain, Aanchal Sachdeva and Sundararajan A. It focused on the benefits of Cadence Xcelium Logic Simulation with machine learning technology (Xcelium ML) in achieving compression in terms of CPU hours and faster regression throughput while withholding the behavior of regression and achieving the desired coverage efficiently was presented in this tutorial.

Verification management tools such as ranking and coverage correlation to achieve the coverage goals faster and thereby improving overall regression throughput suffer from challenges like failing to hit new coverage or identifying new bugs. 

It creates models and helps in creating optimized regressions w.r.t user-defined goals such as compressing the full regression, targeting specific areas of coverage space, hitting target space at a higher rate while retaining the behavior of regression

The table shows customers achieving effective compression 3X to 5X however it may be as high as 10X and as low as 2X as well and coverage regain is from 98% to ~100%. Xcelium ML optimized the number of regressions runs from 10042 to 1279 thereby achieving 7.8X and was able to regain 97% coverage when employed during early stages.

Regression runs optimized from 4800 to 1200, 31 new bins were created was achieved when employed in later stages.