Join Cadence at DVCon India 2021 Next Week!

It's almost time for the event that Design and Verification engineers have been waiting for - DVCon India. Now in the 6th year, the Design and Verification Conference, or DVCon, is one of the premier industry conferences that can't be missed. Verification experts will share their technical contributions in the areas of Verification & Validation, Methodology & Automation, Functional Safety & Security, Low Power and Mixed Signal Design, Static and Formal methods, Digital Twins and SystemC Modelling.

Scheduled from 14-16 December, the virtual conference will feature a mix of keynote talks, panel discussions, tutorials, and workshops as well as 24 user papers and 16 poster sessions. This year has seen a record number of submissions to the conference. 
 

Cadence is proud to be a global sponsor of DVCon, and in addition we are presenting the following sessions at the event. 

• Tutorial 2.1: Achieve Faster Regression Throughput by Applying Machine Learning and Advanced Technologies
  Tuesday, December 14, 11:30 – 13:00, Track 2
• Tutorial 2.2: Benefits of a Common Methodology for Emulation and Prototyping
  Wednesday, December 15, 9:30 – 11:00, Track 2
• Paper 3.6: An Approach to Overcome Modeling Inaccuracies for Performance, Simulation Signoff of High-Speed SerDes
  Thursday, December 16, 9:55 – 10:20, Track 3  
• Panel: Today's SoC Verification Challenges and Solutions. Panelists include Vivek Kashyap from Google, Nirmal Arumugam from Qualcomm, Pankaj Kakkar from Cadence, Sukumar S Raghuram from Intel and is moderated by Nick Heaton, Distinguished Engineer at Cadence.
  Thursday, December 16, 11:30 – 12:30

 If you haven't already done so, register today at https://dvcon-india.org/registration/

See you next week!