My Journey - From a Layout Designer to an Application Engineer

Today, we are living in the era where whatever we think of as an idea is not far from being implemented…thanks to machine learning (ML) and artificial intelligence (AI) entering into the semiconductor industry.

In this blog, I want to share my experience of being an AE (application engineer) for the last 6+ years in designing memory layouts. I will also be talking about some of the changes that have taken place in the layout development methodology for continuously improving turn-around time (TAT).

The importance of turn-around time

In recent years, semiconductor manufacturing has become extremely complex due to device size reduction. Hence the manufacturing cycle time, also called turn-around time, which is defined as the time required from architectural design through verification and implementation to the manufacturing cycle, becomes longer year by year. On the other hand, customer demands for faster delivery are increasing because their product life cycles are getting shorter. Therefore, TAT reduction is important for semiconductor manufacturers not only to satisfy customer requirements, but also to remain competitive in the market. 

With the advancement in EDA (Electronic Design automation) tools required to design electronics system such as Integrated Circuits and Printed Circuit Boards, TAT has reduced significantly. I remember when I started my career in VLSI, for any scratch (new) development of a memory compiler for a basic configuration, it used to be somewhere between nine and twelve months. Now it’s just a quarter of that time, or sometimes even less.  Advanced Layout methodologies like design planner analysis, Concurrent Layout Editing, simulation driven routing, multi patterning, smart in-Design Rule Checking (DRC) etc have greatly accelerated TAT and made the layout designer’s life easier.

How advanced automation can help

I’ll share two examples.

First, let’s take an example of a global control block in a memory compiler. It is one of most complex blocks in terms of logic. Its function is to buffer the address signals received from the external world and drive the row decoders and column multiplexers to point to the required memory cell. In addition to that, it plays a significant role in driving other blocks in the compiler such as sense amplifier and output drivers. It consists of critical signals such as CLK which require proper shielding. Thus, there are many factors which need to be considered while doing layout for this cell.

With this type of detailing, it used to take more than a month to complete this single block. But today, it can be completed in 2-3 weeks, thanks to advanced interactive layout technologies such as in-design DRC, in-design LVS (Layout vs Schematic checks), in-design Resistance & Capacitance calculation, schematic driven layouts, etc. But that leap to switch from the traditional, manual flow to automated tools, has to be initiated by the layout designer.

The second example is with Electrical Rule Checking (ERC). ERC is a methodology used to check the robustness of a design both at schematic and layout levels against various design rules. These design rules are often project-specific and developed based on knowledge from previous tape-outs or in anticipation of potential new failures. Not complying with these rules can result in reduced yield, defect escapes to customers, and delayed failures in the field. Thus design robustness is compromised when ERC is not enforced.

One of the rules in ERC includes checking net area ratio for antenna rules. In analog layout designs, we are concerned about process antennas which are the long metal geometries connected between the gate of one device to the Source/Drain terminal of the other device. It also tends to accumulate charge during the fabrication process. These long antennas can affect the transistor’s threshold voltage in extreme cases. This is one of the several tricky design pitfalls that can be avoided with the use of automation.

If automating the layout design can be so beneficial, why do layout designers not take this route more often? Usually, it’s because learning a new methodology requires time and effort, and designers either don’t have the time or the inclination to invest into learning something new. This results into more man-hours, increased stress and more importantly potentially impacting the project cycle.

Role of an Application Engineer

As designers start to use advanced automated technologies, the support of the Application Engineer (AE) is a great benefit. AE's act as a catalyst in new technology adoption, and also play a vital role in demonstrating the application of tools and utilities to solve the complex design requirements to the customer.

Throughout my experience as an AE, many times I have seen how trust builds up with the customer when an AE is able to save their time and effort by helping them use the tools and features smartly. It is a tremendously satisfying moment when the AE and the customer work together overcome a design challenge. This kind of collaboration is key to the success of an AE.

I believe that AE's bridge the gap between innovation and effective tool utilisation. The real high for the AE is when the chip gets taped out with first silicon success, and it is deployed in a product. That’s what makes all the hours and days of effort worthwhile.