We Have Winners! … Of The CadenceLIVE 2020 India Best Presentation Award

23 Sep 2020 • 1 minute read

CadenceLIVE 2020 India, our first digital conference held on 9-10 September and what an event it was! With 75 technical paper presentations, four keynotes, a virtual exhibition area, and fun gamification, CadenceLIVE once again proved to be one of the premier industry conferences.

Best Presentation Award

The Best Presentation Award has been an important part of the CadenceLIVE (CDNLive) Conference since 2005. We give this award to acknowledge and appreciate the efforts of the authors. In previous years we have announced the best paper award at the end of the conference, but this year presenters had to wait few days to know the results of their presentations.

One best paper was chosen in each of the event's nine session tracks. The presentations were judged by an expert committee comprised of seasoned professionals from both Cadence and its customer base. The criteria for judging the presentations were originality, relevance to the design community, Cadence technology use, and presentation.

The best paper award winners in each of the technology track are:

Track	Paper Title	Company
Digital Front-End Design	Efficient Handling of Super Under Drive Corner with Genus iSpatial at Lower Tech Nodes	Samsung
Digital Implementation and Signoff	A Cookbook for Aggressive Area Reduction Strategy on Arm Cortex-A55 CPU Core Using Cadence Implementation, Power, and Signoff Solutions	Arm
Custom and Analog Design: Verification	Advanced Methodology for Accurate EM-IR Analysis in Voltus-Fi XL	Texas Instruments
Custom and Analog Design: Implementation	CLE (Concurrent Layout Editing), a New “Advanced” Methodology for the Next Generation of MSoT Smart Power (BCD) Design	STMicroelectronics
Advanced Verification Methodology	Functional Verification of C++ Models for DDR Controller	Google
Performance and Smart Bug Hunting	Accelerating SoC Verification Signoff Using SNR/DTR Enhanced Regression Flow	Samsung
System Design and Verification: Flows	Efficient Fault Injection Methodology for ASIL-D-Compliant Automotive SoCs	STMicroelectronics
System Design and Verification: Emulation and Prototyping	Improving Firmware Validation Productivity and Debug Efficiency Using Palladium Z1 Platform and Indago Debug Analyzer	Analog Devices
PCB Design and System Analysis	Modeling and Simulation Challenges of DDR5/LPDDR5 Interfaces and Enabling DFE Techniques Using Sigrity Technology	Mobiveil

Congratulations to all the winners!

If you missed attending CadenceLIVE India, you can still watch most of the sessions on-demand.