Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
You read stories about it – the device or chip that comes out and consumes more power than expected. Maybe the battery life isn’t what it was supposed to be (my current smartphone is a great example!). Or even worse, maybe there are failures because the excessive power density generates too much heat for the chosen package or heat dissipation method. These stories get around because, well, product recalls tend to. Of course, we don’t even hear about all the chips that were over-spec’ed for power. Yes, given the above it is prudent to err on the side of caution. But with a high-volume chip, the extra $1.00-$1.50 for the “safe” package or heat sink can really make a dent in the bottom line. The root of this all is that these types of decisions are typically made very early in the project, long before you can test the chip in the lab to see what the real power consumption is. As a logic designer, what can you do about it? Is it even your problem?
To answer the latter question, it really has become everyone’s problem. To be successful, you need to constantly measure it and refine the model, re-visiting those early decisions (product specs, package specs, project profitability, etc) course-correcting as necessary. But what can you do about it? The obvious answer is to measure it as early and often as possible. But how do you get accurate power estimation during the logic design stage? The software is going to have a huge effect that will vary over time – how do you account for that during logic design? Physical timing closure has a large effect on power consumption – think about all those wire capacitances and all the cell swapping that goes on. The clock tree often accounts for a large amount of power consumption….what do you do about that? The problem is that you do need to know the answers to these questions as early as possible to make decisions such as whether to use techniques like power shutoff or multi-supply multi-voltage, etc. You even need these answers as early as the decision-making process for what library, IP’s, and memories you will use. As the project goes on, you can reduce the uncertainty more, and make adjustments as necessary. But during logic design there is still a lot of uncertainty…it would be interesting to hear what folks do to reduce that. How do you look ahead and get better power estimates while you’re doing logic design? How do you make good estimates to drive the heat dissipation decisions? And to the makers of my phone (not naming names!), how can you make adjustments for the next generation so the battery life is better? I’ll roll up and post the best suggestions from the comments as well as some suggestions of best practices that we’ve seen out there.