Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
The blog referenced above states that physical synthesist tools require a logic designer to learn physical design details, learn new tools, and co-ordinate with the physical designer. While I agree that all this is true, I see it as an advantage and not a disadvantage. In my discussions with customers it has become clear that iterations between front-end and back-end teams have become a complete nightmare and can cause significant schedule and TTM delays. In response to this problem many design teams use extremely conservative wireload models and over-constrain their design to the point of absurdity. While this may alleviate the iterations, it clearly causes design to be bloated in terms of area and power, both of which cost money. So my first question to you and the rest of the community is, Isn’t it better to understand the real physical effects upfront to allow a more realistic design to be handed off to the physical design team? Even at the expense of a learning curve for the front-end team ?
I also want to address the issue of runtime, and especially wasted runtime. While it is true that there is a runtime overhead to run a physical synthesis flow, this is easily mitigated by the reductions in iterations between the front-end and back-end design teams. In addition to that, the RC-Physical technology, which was not mentioned in your article, allows a front-end team to hand-off full legal placement to the backend team so that the up-front effort is in fact not wasted at all. While there is still some optimization required in the physical design tools, our experimentation has shown that the amount of time spent is greatly reduced in a true physical synthesis flow.
Finally, comments were made about WLM based synthesis being well understood and mature. My contention is that is indeed well understood, understood to be outdated and inaccurate. There is no way that a WLM based flow can accurately predict wire effects in modern designs due to both small geometries and large blocks. Is using this antiquated methodology a good thing just because it has been used for so long?
And now a final comment about accessibility and affordability, on this comment I cannot agree more. If you look at the Cadence physical synthesis solution, it is really a tiered solution that allows a design team to make this exact trade-off. The base RTL-Compiler technology includes two technologies for predicting wires in the design. The first is Physical Layout Estimators (PLE). This has the simplest use model and only requires a user to read in the LEF files and capTable for their chosen technology. A floorplan can be used for defining the aspect ratio of the block. The second technology is the RC-Spatial technology mentioned in the blog. RCS allows the user to add a quick placement to the synthesis flow in order to better predict the wires in the design. In this case the floorplan is highly recommended as it will greatly increase the accuracy of the prediction as well as the Quality of Silicon (QoS). Both of these technologies are predictive in nature and by definition are not 100% accurate with respect to the actual final physical design. For those designs that want the closest correlation with P&R, the highest level of QoS, and the ability to analyze and optimize for real congestion, Cadence provides a separate product called RC-Physical. This product uses real production placement and includes native congestion analysis and optimization. It is really the Cadillac of physical synthesis tools.
I hope that this response clears up some of the comments and helps readers to understand the current state of physically aware synthesis at Cadence.
This commnets help me a lot. Thanks...