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The blog referenced above states that physical synthesist tools require a logic designer to learn physical design details, learn new tools, and co-ordinate with the physical designer. While I agree that all this is true, I see it as an advantage and not a disadvantage. In my discussions with customers it has become clear that iterations between front-end and back-end teams have become a complete nightmare and can cause significant schedule and TTM delays. In response to this problem many design teams use extremely conservative wireload models and over-constrain their design to the point of absurdity. While this may alleviate the iterations, it clearly causes design to be bloated in terms of area and power, both of which cost money. So my first question to you and the rest of the community is, Isn’t it better to understand the real physical effects upfront to allow a more realistic design to be handed off to the physical design team? Even at the expense of a learning curve for the front-end team ?
I also want to address the issue of runtime, and especially wasted runtime. While it is true that there is a runtime overhead to run a physical synthesis flow, this is easily mitigated by the reductions in iterations between the front-end and back-end design teams. In addition to that, the RC-Physical technology, which was not mentioned in your article, allows a front-end team to hand-off full legal placement to the backend team so that the up-front effort is in fact not wasted at all. While there is still some optimization required in the physical design tools, our experimentation has shown that the amount of time spent is greatly reduced in a true physical synthesis flow.
Finally, comments were made about WLM based synthesis being well understood and mature. My contention is that is indeed well understood, understood to be outdated and inaccurate. There is no way that a WLM based flow can accurately predict wire effects in modern designs due to both small geometries and large blocks. Is using this antiquated methodology a good thing just because it has been used for so long?
And now a final comment about accessibility and affordability, on this comment I cannot agree more. If you look at the Cadence physical synthesis solution, it is really a tiered solution that allows a design team to make this exact trade-off. The base RTL-Compiler technology includes two technologies for predicting wires in the design. The first is Physical Layout Estimators (PLE). This has the simplest use model and only requires a user to read in the LEF files and capTable for their chosen technology. A floorplan can be used for defining the aspect ratio of the block. The second technology is the RC-Spatial technology mentioned in the blog. RCS allows the user to add a quick placement to the synthesis flow in order to better predict the wires in the design. In this case the floorplan is highly recommended as it will greatly increase the accuracy of the prediction as well as the Quality of Silicon (QoS). Both of these technologies are predictive in nature and by definition are not 100% accurate with respect to the actual final physical design. For those designs that want the closest correlation with P&R, the highest level of QoS, and the ability to analyze and optimize for real congestion, Cadence provides a separate product called RC-Physical. This product uses real production placement and includes native congestion analysis and optimization. It is really the Cadillac of physical synthesis tools.
I hope that this response clears up some of the comments and helps readers to understand the current state of physically aware synthesis at Cadence.
This commnets help me a lot. Thanks...