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Just a short note for those who will be attending the exciting 22nd International conference on VLSI design in India.
Don't miss Dr. Qi Wang of Cadence, Senior Architect, who co-authored a paper and is co-presenting at this event @ 9am !
Location: New Delhi, India
Date: January 8, 2009
Session: Power Reduction Techniques and
Flows at RTL and System Level
Qi has been a key contributor in defining low power standards for the ASIC design community worldwide. He is part of Si2's Low Power Coalition Steering Committee.
This tutorial is a great opportunity to listen to one of the best sources for ASIC Low Power vision and the intricate details, as well as ask questions directly.
Hope to see you at the event!