Low Power Blogs

It's that time of year again - winding down towards the end of the year, taking some time with the family, and looking forward to returning refreshed for a new year. So what was the big news for low power in 2011 and what do we have to look forward to in 2012? It's sometimes humbling to look at one's own technology predictions and see how things fared a year or so further on. Sometime in 2010, I forget exactly when,...

Here in the USA, we're just back from the Thanksgiving holiday. This year, I got caught up in "Black Friday," which is the day after Thanksgiving, and one of the biggest shopping days of the year, especially for consumer electronics. I'm afraid to say I was convinced enough by some compelling advertising for Black Friday sales to brave the crowds to get a new large-screen HDTV. Doing some minimal research, I had...

Recently, the Silicon Integration Initiative (Si2) announced the availability of the Interoperability Guide for Power Format Standards V2.0 . This is an important milestone of power format interoperability between IEEE 1801-2009 and the Common Power Format (CPF). This update was triggered by the Si2's CPF 2.0 release earlier this year. CPF 2.0 is a major CPF release on top of the previous CPF 1.1 and 1.0 releases. Many...

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Ann Mutschler blogged in the Low-Power Engineering Community that gate-level simulation is coming back, driven in part by low-power verification needs. “In a small sense, what’s old is new” may actually be the biggest understatement in her blog. Ann attributes the observation to Cadence’s Pete Hardee who sees low-power architectural and synchronization dependencies that require gate-level details for proper verification...

In the last five years since the introduction of power formats, using a side file to describe power intent such as power domains, power modes and associated interface logic has become the mainstream low power design methodology. This marks great progress toward automating complex low power design techniques, but our job is not done. A recent interview by Ed Sperling with Sorin Dobre of Qualcomm, posted on the Low...

Low power design was undoubtedly one of the themes of DAC this year -- especially at the Cadence booth. We drew lively interest on the DAC floor with our low power demo station, which was continuously busy especially on the free Monday. We were showing a new demo explaining how advanced low power techniques ("advanced" means the kind of techniques you need a power intent format to describe -- more on this later...

Power was clearly a hot topic at the recent Design Automation Conference (DAC). Many companies demonstrated their unique tool capabilities to address power issues at different abstraction levels. However, we saw very few presentations that offered a user perspective on how they do low power designs and how EDA tools help. The presentation by Alex Kuo from Global Unichip Inc., at the EDA360 Theater in the Cadence booth...

As the clock for the 48 th Design Automation Conference (DAC) ticks away, we at Cadence are scrambling to put the final touch-up on all our DAC activities. Even though my time is limited, I still would like to highlight the significance of two recent and seemingly unrelated events. First is a post at Deepchip.com on some user experiences with the Cadence Encounter® RTL-Compiler synthesis tool. In this post, two anonymous...

While there are multiple techniques for reducing power consumption, shutting off power domains is the main method used to reduce leakage power consumption. In power shut-off designs, there are multiple aspects designers need to take care of, including IR drop, turn-on time, rush current, and the number of power switches added. An earlier post in this Low Power blog, How Easy Is It to Switch Off Power? explored some of...

How easy is it to switch off power? "Honey, could you please make sure all the lights are off before going to bed?" Although I am always wondering why I have to be one to do this, I do not have too many complaints as it is a job of simply flipping a switch. Low power designers wish that designing a chip with power shutoff could be as simple as flipping a switch! The idea of power shutoff in chip design is like having...

Back in December, I wrote a blog entry entitled " Perspective on Power - 300 Designers and 20,000 Miles Later... ". After the latest leg of my travels last week, taking our EDA360 Tech on Tour Low Power Symposium on the road to Taiwan and Japan, I intended to write an update to that blog article. Clearly, the trip was overshadowed by recent events in Japan. The week started great -- I arrived at Taipei Airport...

The long awaited new version of the Common Power Format, CPF 2.0, was released by the Silicon Integration Initiative ( Si2 ), an industry standards organization, today. Here are several interesting observations from this latest release . First of all, this new release is a big step forward for interoperability between IEEE 1801 (Unified Power Format 2.0), the other industry power intent format, and CPF. In 2009...

If you're like me, one of the things you appreciate about traveling is the contrasts. It's great to experience the different cultures, geography, architecture and cuisines across the world. It's the differences that make it exciting. It was fun to experience those differences once again as, for the first time in a while, I had a series of road trips taking me to seven major cities across North America, Europe and...

You've been building chips for years and the growing complexity means you just can't tolerate simple tool-to-tool flows and group-to-group barriers any more. SystemC and RTL in the same low-power simulation? Got it. Mixed-signal? Yep. Every team with fingers in the power intent? For sure. Siicon Realization is real to you because you're living it, but you need more from EDA so you're demanding "Cadence Low-power...

Today I'd like to dive into one of the topics I mentioned in my blog in August -- measuring chip power. This seems to be one of the questions I get from many people. How can a design team effectively measure power all throughout the design flow, with the key phrase being "throughout the entire flow"? Power measurement requirements have evolved over the years from rough estimations to the need to have more precise power...

This is the final posting in a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will talk about concepts behind digital-centric mixed-signal verification (DMSV). My previous blogs covered some of the following topics: 1. Basics of dynamic power management 2. Very brief introduction to RNM (Real Number Modeling) for efficient simulation of mixed signal...

This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will cover metrics collection from analog circuits during mixed-signal simulation. My previous blogs covered some of the following topics: 1. Basics of dynamic power management 2. Very brief introduction to RNM (Real Number Modeling) for efficient simulation of mixed signal...

This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will cover error detection. My previous blogs covered some of the following topics: 1. Basics of dynamic power management 2. Very brief introduction to RNM (Real Number Modeling) for efficient simulation of mixed signal SoCs 3. How to create a controlled voltage source using...

This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I'll discuss the simulation of closed-loop voltage scaling for adaptive dynamic voltage and frequency scaling (DVFS). My previous blogs covered some of the following topics: 1. Basics of dynamic power management 2. Very brief introduction to RNM (Real Number Modeling...

So you're about to start your first low power design. Or second, third, or fourth. As with many tapeouts, you know that with today's tight market windows, most likely the project will go off with a sprinting start (architectural planning), followed by an endurance test (designing and implementing), then a final mad dash towards the finish line (signoff closure and tapeout). First, the bad news - given the complexities...

This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I'll discuss open-loop and closed-loop voltage scaling. In previous blogs, I covered some of the following topics: Basics of dynamic power management Very brief introduction to RNM (Real Number Modeling) for efficient simulation of mixed signal SoCs How to create...

The notion that your ability to analyze power dissipation more accurately as your design proceeds down the levels of abstraction from system-level, to RTL, and to gate-level and transistor-level netlist has existed unchallenged for too long. Well, would I be tilting at windmills to challenge it? I could bore you all with the math, but fundamentally, dynamic power boils down to be a function of two things -...

Power intent formats exist to express the design's low power techniques separately from the design's functional description. This promotes portability of the design across different power schemes. So why are most commercial IP providers forced to bury this critical information deep in gate-level simulation models and library files? Advanced low power design techniques, such as Power Shut-Off (PSO) with or without...