Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Ann Mutschler blogged in the Low-Power Engineering Community that gate-level simulation is coming back, driven in part by low-power verification needs. “In a small sense, what’s old is new” may actually be the biggest understatement in her blog.
Ann attributes the observation to Cadence’s Pete Hardee who sees low-power architectural and synchronization dependencies that require gate-level details for proper verification. While gate simulation itself is an old general verification concept, the underlying need for accuracy has never gone out of style. When most of the projects shifted to more synchronous designs in the middle and late 1990s, there was some talk about higher-level sign-off. However, the increased integration of analog and low-power, especially where there are multiple clock domains, introduced new sources for asynchronous stimulus/response which required the accuracy of gate simulation to verify.
The understatement is that modern gate-level simulation is just driven by these new sources of asynchronicity. The reality is that low-power opens a whole new dimension of accuracy that Verilog (or VHDL/Vital) was never built to accommodate. Truly accurate low-power simulation needs to model the shutdown corruption on domain inputs so that the simulation engine does not clear unknowns from the shutdown domain prematurely. Another example is that the physical location of isolation and the delays on the isolation nets must be modeled to mimic silicon -- otherwise the simulator may not arrive at the right isolation values as it resolves the net values at a given point in time.
On top of effects like these, Pete states the value of static formal checking. However, it’s not just gate to RTL equivalence that is important -- gate simulation to implementation checking is also needed for the low-power modeling. So it’s not just a "small sense" that what’s old is new, but a significant new requirement that demands the accuracy only found in gate-level simulation to produce working silicon.
Have you recently found the need for more gate simulation? If so, please share your experiences on what keeps gate simulation a key part of your verification process.
=Adam "low-power doesn't mean low-key" Sherer
Adam, apologies for being really late in replying. Missed your response. I have been an avid user of Incisive. Infact have seen the tool mature from 130nm till date :) The debugging capabilities are excellent!
Your blogs do provide a good background for gate-level simulation. I would encourage you and your readers to explore the Incisive Enterprise Simulator as well. Cadence invented most of the features you describe in your 3 posts. In addition, we have several techniques to make the "necessary evils" you describe a lot less evil. One of those is a great signal tracing capability in our own debugging tool SimVision. Feel free to take a look at these links and blog about it on your WhatIsVerification.
And with this one you could even add FSM mnemonics onto your traces to help with debug:
We have many gate-level users at and below 40nm which leads us to innovate features that benefit all users.
A quick summary on the need for GLS -