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ARM-Based Microcontrollers using Cadence’s Mixed-Signal Solution

By Sathish Bala | 25 Sep 2012

I recently came across a Wall Street Journal article, "ARM Chases Bigger Slice of Smaller Chips," that provides a very interesting perspective on how ARM is positioned to capture the microcontroller market, which is its next growth area. ARM based microprocessors are clearly dominating the mobile products from smart phones to tablets across Windows, Android and IOS mobile eco-systems. Most of these devices are using...

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DAC | microcontrollers | Demo | Cortex-M | MCUs | Virtuoso | Cortex-M0 | incyte | fuel injection system | System Design Kit | micro-controllers | ARM | Balasubramanian
Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM

By Sathish Bala | 27 Aug 2012

Even though it's been over 2 months since this year's Design Automation Conference in San Francisco, I am still surprised by the response that metric-driven, mixed-signal verification gets from our design community. Cadence had quite a few customer presentations at the EDA360 Theater at DAC this year. However, there was one presentation titled "Metric Driven Verification Approach for Analog/Mixed Signal IPs" authored...

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real number modeling | DAC | uvm | IP | A/MS | Verilog-AMS | analog | co-simulation | Mixed-Signal | analog behavioral models | analog/mixed-signal | model validation | RNM | metric-driven verification | VHDL-AMS | assertions | mixed signal | mixed-signal design | wreal | real number models | Design Automation Conference | SPICE | mixed-signal verification | verification | stmicroelectronics | real number
Mixed-Signal Gets Clear Message in China

By QiWang | 10 Jul 2012

While most of my colleagues in the US were taking a nice break during the July 4 th week, a small group of people including me was on the road for a mixed-signal Tech-on-Tour in China. There was some debate internally on whether designers in China would be interested in such a topic. What we had experienced last week was a clear (not mixed) signal from the IC designer community in China that they are hungry for knowledge...

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mixed-signal seminars | Beijing | AMS | China | mixed signal design | Technology on tour | mixed-signal ToT | mixed-signal methodology | mixed signal methodology | tech on tour | mixed signal solution | analog | Mixed-Signal | Shenzhen | mixed signal methodology guide | mixed signal | ARM | tech-on-tour | Shanghai | AMS Verification | mixed-signal verification
Tech-On-Tour: Bringing Advanced Mixed-Signal Design Methodology from Concepts to Reality

By QiWang | 19 Jun 2012

About a year ago, Cadence offered a worldwide Tech-On-Tour (ToT) series for mixed-signal designs. One main objective of this seminar series is to bring the awareness of the need for a design methodology change to the broad mixed-signal designer community worldwide. The event was very successful and you can find some previous blog coverage here: M/S Technology on Tour Blog - Model Validation and Assertion Based Verification...

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DAC | Technology on tour | mixed-signal methodology | tech on tour | CPF | Mixed-Signal | encounter | Virtuoso | Cortex-M0 | incyte | mixed signal | Mixed-Signal Methodology Book | tech-on-tour | OpenAccess
What’s Hot for Mixed-Signal At DAC?

By QiWang | 31 May 2012

Analog/mixed-signal design is a hot topic at the Design Automation Conference! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), you can keep up with the latest developments in mixed-signal design methodology, including design, implementation and verification. You will find it is very hard to choose from so many options. Here is a quick guide to presentations, demos and other events Cadence is involved...

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DAC | AMS | mixed signal design | mixed-signal methodology | mixed signal methodology | mixed signal solution | 28nm | 20nm | Advanced Node | Low-Power | Mixed-Signal | mixed signal physical implementation open access | mixed-signal book | mixed signal methodology guide | low-power design | mixed signal | cortex M | mixed-signal design | power | Design Automation Conference | mixed signal implementation | digitally assisted analog | mixed-signal verification
Cadence To Release the Industry's First Mixed-Signal Methodology Book

By QiWang | 26 May 2012

The new era of “Internet Everywhere” creates a whole new spectrum of applications, ranging from health care, automotive, to entertainment and cloud computing, which demand more and more mixed-signal and low power designs. In fact, mixed-signal applications have become one of the fastest growing segments in the electronics and semiconductor industry. Traditional mixed-signal designs treat the analog and digital designs...

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AMS | mixed signal design | mixed-signal methodology | mixed signal methodology | mixed signal solution | analog | Mixed-Signal | mixed-signal book | dac2012 | mixed signal methodology guide | Mixed signal physical implementation | DAC 2012 | mixed-signal design | mixed signal implementation | mixed-signal verification
Managing Inherited Connections with CPF in Virtuoso

By AndreasLenz | 23 May 2012

Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist needs to be imported into Virtuoso. Why use CPF? The Common Power Format (CPF) describes the design power intent for the whole...

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inherited connections | EDI | Low Power | mixed signal solution | CPF | analog | Mixed-Signal | encounter | Verilog | mixed signal physical implementation open access | Virtuoso | oa | Mixed signal physical implementation | mixed signal | OA: OpenAccess | mixed-signal design | Virtuoso environment | mixed signal implementation | design implementation | Common Power Format
A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs

By paragb | 16 May 2012

The purpose for creating a Pcell is to automate the creation of data. Pcells should be designed as standalone entities, independent of the environment in which they are created and independent of the variety of environments in which you or someone else might want to use them. An environment can react to a Pcell, but Pcell code should not react to, interact with, or be dependent on an environment. Although it is possible...

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ECO | Static timing analysis | EDI | mixed signal design | parasitic | IC 6.1 | mixed signal solution | Open Access | STA | timing model | ECOs | mixed-signal ECOs | Mixed-Signal | encounter | Virtuoso | oa | EDIS | ECOs and PCells | Mixed signal physical implementation | mixed signal | signoff | OpenAccess | Virtuoso environment | mixed signal implementation
What is Digitally Assisted Analog Design?

By QiWang | 30 Apr 2012

Mixed-signal applications are among the fastest growing segments in the electronics and semiconductor industry. Applications in mobile communication, networking, power management, automotive, medical, imaging, safety and security require a very high integration of analog and digital functionality at system, SoC and IP levels. Unfortunately, compared with the advancement of digital designs over the past decade, the state...

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daa | AMS | Low Power | mixed signal design | mixed signal solution | Mixed-Signal | dac2012 | Mixed signal physical implementation | mixed signal | cortex M | DAC 2012 | ARM | boris murmann | digitally assisted analog | mixed-signal verification
CDNLive! -- Real Number Model Development and Application in Mixed-Signal SoC Verification

By AElzeftawi | 9 Apr 2012

With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital content in response to new functionality demands, and steady growth of IP blocks into larger and larger SoCs, traditional AMS verification flows are becoming inefficient in handling full chip verification. High-performance digital verification and high accuracy analog verification represented the foundation for traditional AMS verification...

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real number modeling | CDN Live | CDNLive SV 2012 | CDNLive | AMS Designer | LSI | RNM | behavioral models | CDNLive! | wreal | Luo | Virtuoso environment | AMS Verification | mixed-signal verification | verification
DVCon 2012: Bringing Continuous Domain into SystemVerilog Covergroups

By PrabalB | 30 Mar 2012

On the last day of February 2012, I presented a proposal at the DVCon 2012 Conference to extend SystemVerilog to support a real data type in coverpoint objects in order to facilitate mixed-signal verification for functional coverage. The paper, titled “ Bringing Continuous Domain into SystemVerilog Covergroups, ” reflected a year-long effort between Cadence R&D and Scott Little of Freescale (Scott moved to Intel just...

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SystemVerilog | coverage | covergroups | Functional Verification | analog | Mixed-Signal | DVcon | real number types | functional coverage | mixed signal | floating point | mixed-signal verification | verification | real number
Learn How to Do Mixed-Signal Design at CDNLive! Silicon Valley

By QiWang | 7 Mar 2012

With the theme of Connect, Share and Inspire, this year's CDNLive! Silicon Valley March 13-14, 2012 will be an exciting forum for Cadence customers to share their most recent chip design successes and learn from each other. Among close to 100 presentations during the packed two day agenda, one area stands out is mixed-signal design. There are more than 10 presentations with specific focuses on mixed-signal design challenges...

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real number modeling | APS | Low Power | mixed signal design | CDNLive SV 2012 | parasitic | IC 6.1 | AMS Designer | CPF | analog | Mixed-Signal | analog behavoral | Virtuoso | RNM | CDNLive! | mixed signal | simulation | verification
Virtuoso AMS Designer Wins the China ACE Best EDA Product Award

By QiWang | 28 Feb 2012

The China Annual Creativity in Electronics (ACE) Awards was established to recognize individuals, companies and technologies that have made profound impacts in the overall China electronics industry each year. Joining with the industry prestigious names like ARM and TI, Cadence Virtuoso AMS Designer won the 2012 Best EDA product award. Five candidates were nominated for this award including Cadence. The award was presented...

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AMS | Virtuoso-AMS | China | mixed signal design | ACE award | AMS-Designer | AMS Designer | Mixed-Signal | wreal
Behavioral Model Validation with amsDmv

By xiuya | 30 Nov 2011

a msDmv (Analog Mixed Signal Design and Model Validation) is an application integrated in the Cadence Virtuoso GUI flow and it can also be invoked from command line with some feature limitations. amsDmv can be used to compare the simulation restults and design interface (pins) from the DUT with those from the reference design. Therefore users can use amsDmv to validate behavioral models with original transistor level...

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AMS | Mixed-Signal | analog behavoral | model validation | Virtuoso | behavioral models | mixed signal | amsDMV
Fred Discovers 1000x-10000x Speedup Using wreal Models

By Paul Foster | 1 Nov 2011

This is the second installment in an ongoing series of blog posts that includes an email conversation between Fred and Harry, two fictional mixed-signal engineers, about analog behiavoral modeling. You can read the first installment by clicking here . (NOTE: This blog post was written by Walter Hartong and uploaded by Paul Foster). Hi Harry, As I said, this was really the fun stuff. We are coming into the region of 1000x...

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real value | Verilog-AMS | analog | Mixed-Signal | analog behavoral | Verilog | Virtuoso | Fred | mixed signal | wreal | SPICE
How Fred Discovered Mixed-Signal Behavioral Modeling

By Paul Foster | 31 Oct 2011

Introduction This is the first of a series of blogs where we will add pieces to the story over time. This is an email conversation between Fred and Harry, two fictional mixed-signal designers, where Fred is adopting various modeling techniques to realize faster simulations while maintaining acceptable levels of accuracy. (NOTE: This blog post was written by Walter Hartong and uploaded by Paul Foster). How Fred came to...

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AMS | mixed signal design | AMS-Designer | Verilog-AMS | analog | Mixed-Signal | Virtuoso | Fred | assertions | mixed signal | wreal
Managing ECOs in Mixed Signal Designs

By Benatcdn | 29 Sep 2011

Imagine you are days away from completing the implementation of a fairly complex mixed-signal design, and you are already day-dreaming about the vacation you have planned in a few weeks. Then it happens -- the dreaded change in the design requiring ECOs to digital or analog content, or worse yet, implementation problems that need fixing. Should you call the travel agent to see if you can still buy travel insurance...

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ECO | Farhat | mixed signal design | CPF | Open Access | Floorplanning | ECOs | mixed-signal ECOs | Mixed-Signal | encounter | Virtuoso | oa | Mixed signal physical implementation
Bringing Static Analysis Methods to Mixed Signal Designs

By RajendraPratap | 26 Aug 2011

Accurate static analysis and complete coverage of the functional space remain very challenging for mixed-signal designs. The functional verification of mixed -signal designs has never been completely possible. It is very common to use behavioral models of analog/mixed-signal blocks during the full chip functional verification stage, and to use .lib timin g models during the physical implementation stage. There...

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Static timing analysis | static analysis | mixed signal design | full timing model | STA | timing model | analog | FTM | Mixed-Signal | signal integrity | OpenAccess | SPICE | liberty model | .lib
Synchronizing Designs and Behavioral Models in Mixed-Signal Flows

By Paul Foster | 6 Jul 2011

The creation of behavioral models is only one part of the process of using those models in a mixed-signal design verification flow. If the model and design don't match, the effort is worthless. Even worse, it can damage the entire design verification process. "Why should I care about keeping my behavioral models and designs in synch ?" The benefit of using a bottom-up behavioral model to improve design...

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AMS | Virtuoso-AMS | mixed signal design | AMS-Designer | amsDMVAMS-Designer | Verilog-AMS | analog | Mixed-Signal | model validation | mixed signal | wreal
M/S Technology on Tour Blog – Model Validation and Assertion Based Verification

By PrabalB | 28 Jun 2011

In February 2011, I had the opportunity to meet a group of analog and mixed-signal design and verification engineers in Boston, Austin and Irvine as part of the Cadence Mixed-Signal Tech-on-Tour program . This was a revealing experience for me in many ways. Having been intimately involved with the AMS Designer simulator development for the past 11 years, it was fantastic to see how mixed-signal verification is gaining...

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Virtuoso-AMS | mixed-signal ToT | amsDMVAMS-Designer | Mixed-Signal | SVA | model validation | Virtuoso | PSL | assertions | mixed signal
How to Design Analog/Mixed Signal (AMS) at 28nm

By nizic | 21 Jun 2011

Wireless, networking, storage, computing and FPGA applications have been moving aggressively to advanced process nodes to take advantage of lower power consumption, improved performance and area reduction. Today, most of these applications integrate a significant amount of analog/mixed signal (AMS) or RF together with digital circuits. Since AMS often occupies over 50% of the chip area, applying traditional, conservative...

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AMS | AMS v2.0 | APS | Virtuoso-AMS | IP | AMS-Designer | reference flow | 28nm | TSMC | analog | Mixed-Signal | LDE | Virtuoso | Spectre | mixed signal
Mixed-Signal Physical Design Implementation Made Easy

By RajendraPratap | 16 Jun 2011

Getting a complex mixed-signal design assembled and completely analyzed for mask design is a huge challenge today. The IPs are complex and too many decisions need to be made to meet design budgets. All this is not possible with anything less than a fully automated, front-to-back mixed-signal design solution. On top of mixed-signal complexity, battery operated wireless and hand-held mobile applications are extremely sensitive...

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Low Power | IC 6.1 | Floorplanning | Mixed-Signal | encounter | Virtuoso | mixed signal | OpenAccess | design implementation
CPF Low Power Simulation with Analog and Mixed-Signal Design (CPF-AMS)

By Qingyu Lin | 23 May 2011

We have been talking about low power simulation and the Common Power Format (CPF) for five or six years now. It’s become popular in most digital designs thanks to a mature methodology and design flow. However, more and more SoC designs are coming up with mixed-signal content. How will low power technologies and formats be used in mixed-signal design? For SoC design verification, we always involve an analog solver...

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Low Power | CPF | Verilog-AMS | analog | Mixed-Signal | Spectre | Connect Module | mixed signal | wreal | SPICE
Is China Ready for Next Generation Mixed-signal Design?

By QiWang | 18 Mar 2011

A Chinese design engineer told me that his manager once told him: "You do not have to have creativity but you must know how to imitate!" This is kind of a reflection of the rapid technology growth in China for the past decade, where many of the technology advancements came from learning the latest and best technologies from the West. When we planned for the worldwide Cadence EDA360 Tech-On-Tour mixed-signal seminars...

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China | mixed-signal ToT | tech on tour | abstraction | EDA360 | analog | Mixed-Signal | Convergence | intent | japan | Silicon Realization | mixed signal | SoCs
Advanced Mixed-Signal Designs Demand a Unified Methodology

By nizic | 6 Feb 2011

Mobile, automotive, consumer and medical applications require the productive realization of large and complex mixed-signal systems in silicon, and they must be on time and within budget constraints. Process capabilities make it possible to implement analog and RF circuits in CMOS technology at advanced nodes, and to integrate analog and digital functionality at the system-on-chip (SoC) level. However, mixed-signal SoC...

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conformal | RF | mixed-signal seminars | Low Power | CPF | abstraction | analog | ECOs | Mixed-Signal | Convergence | intent | Silicon Realization | mixed signal | signoff | SoCs

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