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  • AndreasLenz
    IC6.1.6 Virtuoso Space-Based Mixed-Signal Router (VSR)
    By AndreasLenz | 29 Oct 2013
    Virtuoso Space-Based Router (VSR) is routing solution integrated into the Virtuoso Layout Suite, which provides a comprehensive set of routing features for a variety of layout tasks. One major design task for layout designs is chip/block assembly routing in mixed-signal analog top (AoT) designs. What's new in Virtuoso IC6.1.6? VSR routing engines were enhanced to improve routing quality (QoR) and to give better...
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    Tags:
    Technology on tour | MS ToT | VSR | mixed-signal ToT | mixed-signal training | Router | tech on tour | Open Access | analog/mixed-signal | OA: OpenAccess | tech-on-tour
  • Sathish Bala
    Cadence’s Annual Mixed-Signal Summit 2013: A Mind Meld of Mixed-Signal Design Community
    By Sathish Bala | 6 Oct 2013
    If you're a fan of the Star Trek series (my six-year-old son and I watch it together faithfully!), you know the Vulcan Mind Meld. (If you're not a Trekkie, the mind-meld is a process of transferring one's knowledge to another person instantly). Mixed-Signal Technology Summit , Oct. 10 at Cadence's San Jose campus, is the closest thing to a mind meld to share mixed-signal design practices and challenges among the design...
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    Tags:
    IP | cadence | AMS Designer | SV-DC | Incisive | SV-RNM | DMS | Virtuoso | mixed-signal book | mixed-signal summit | RNM | mixed signal
  • Sathish Bala
    Coming Soon: Asia-Pacific Mixed Signal Summit and Tech-On-Tour Events
    By Sathish Bala | 15 Jul 2013
    Cadence is bringing the Analog/Mixed-Signal Summit to Shenzhen, China, and the Mixed-Signal/Low-Power Focused Technology-On-Tours to Penang and Singapore later in July 2013. Cadence will showcase mixed-signal and low-power solutions aimed at designs that cater to the always connected world. With smart devices taking over our everyday lives, design teams are moving towards complex mixed-signal designs with advanced low...
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    conformal | SystemVerilog | EAD | AMS | EDI | Low Power | IP | Penang | Technology on tour | mixed-signal ToT | Cadence events | tech on tour | AMS Designer | behavioral modeling | Encounter Digital Implemenation | Advanced Node | analog | Incisive | Shenzhen | LDE | analog/mixed-signal | Virtuoso | mixed-signal summit | RNM | mixed signal | SMG | Cadence Community | Singapore | verification
  • Sathish Bala
    OpenAccess (OA) Based Flow - Efficient Implementation of Mixed-Signal Design for Smart Devices
    By Sathish Bala | 28 Jun 2013
    I had the great opportunity to represent Cadence at the Design Automation Conference (DAC) at Austin a few weeks back. In my role as a Mixed-Signal Solutions evangelist at Cadence, I was thoroughly amazed by the excitement from the ever growing design community at this year's DAC. For Cadence, this was an excellent opportunity to showcase the various technologies covering system, IP and SoC designs. A common theme...
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    Tags:
    Solutions | DAC | cadence | Analog-Centric | Austin | Open Access | analog | VDI | Digital-Centric | Virtuoso | digital | oa | Encounter Digital Implementation | mixed signal | Texas Instruments | Mixed-Signal Methodology Book
  • Sathish Bala
    Mixed-Signal -- Successful Tech-on-Tours, Huge Focus at DAC 2013
    By Sathish Bala | 31 May 2013
    We just completed some hugely successful Mixed-Signal Tech-on-Tours in North America. I am back in San Jose after this whirlwind trip that covered 9 cities in 4 weeks. Even though being on the road does get tedious, what kept me excited was the enthusiasm shown among Cadence customers for the Mixed-Signal Tech-on-Tour events. Close to 400 customers attended these Mixed-Signal Tech-On-Tour events. The Dallas Mixed...
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    Tags:
    real number modeling | clp | AMS Designer | CPF | Conformal Low Power | DAC 2013 | Mixed-Signal | Virtuoso | Internet of Things | amsDmvmv | mobile | PIEA | mixed signal | wreal | SMG | MDV | Schematic Model Generator | ARM Cortex-M | verification
  • Sathish Bala
    Unleashing Mixed-Signal Tech on Tours (ToTs) in North America
    By Sathish Bala | 29 Mar 2013
    At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two days. Cadence customers including IBM, Texas Instruments, Maxim and Freescale shared their mixed-signal methodologies and tricks with the Cadence design community. The key challenges that our mixed-signal customers face are in SoC level verification and seamless analog/digital implementation. Cadence has been addressing these challenges...
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    Tags:
    AMS | EDI | CDNLive | CDNLive 2013 | MS ToT | cadence | tech on tour | mixed-signal IP | AMS Designer | analog | analog behavioral models | analog/mixed-signal | Virtuoso | mixed signal methodology guide | mixed signal | CDNLive SV 2013 | OpenAccess | SoCs | AMS Verification | mixed-signal verification
  • Sathish Bala
    "Smart Devices" and How They Affect Your Mixed-Signal SOC Verification
    By Sathish Bala | 25 Feb 2013
    We are seeing a huge trend -- the mobile revolution is changing the way we go about our everyday lives. Gone are the days where the term 'Internet' was associated with a PC or Mac. The smartphone revolution has changed how the data is consumed and used by consumers and businesses. For example, with the new line of smart systems, every device or appliance is connected to the Internet to manage their services in a better...
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    Tags:
    AMS | DVCon 2013 | CDNLive 2013 | SV-DC | Verilog-AMS | analog | Incisive | Mixed-Signal | smart devices | analog behavioral models | analog/mixed-signal | Virtuoso | Internet of Things | RNM | Verilog AMS | mixed signal | SenseAware | wreal | Virtuoso environment | Schematic Model Generator | mixed-signal verification
  • Sathish Bala
    Revamped Mixed-Signal Solutions Portal Reflects Cadence Leadership and Commitment
    By Sathish Bala | 8 Jan 2013
    Cadence holds a leading position in the EDA industry due to its broad product portfolio catering to digital and analog designs and the ever popular mixed-signal designs. With its immense technical and market leadership based on the Virtuoso platform for analog design and Encounter platform for digital design , Cadence EDA products helps designers achieve productivity gains and predictable design closure for today's complex...
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    Tags:
    CDNLive | cadence | AMS Designer | custom | Design Challenges | analog | web page | Mixed-Signal Methodology Guide | Mixed-Signal | Mixed-signal solutions web page | Virtuoso | mixed-signal book | digital | implementation | mixed signal | Encounter Digital Platform | web site | verification
  • nizic
    Mixed Signal Technology Summit Proceedings Now Available
    By nizic | 13 Dec 2012
    In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased design activities in the mixed-signal area. Attendees used the opportunity to ask questions, share experiences and network. Dr. Chi-Ping Hsu, Cadence Senior Vice president...
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    Tags:
    Static timing analysis | mixed-signal seminars | AMS | static analysis | EDI | microcontrollers | ARM Cortex M0 | mixed signal design | cadence | Functional Verification | mixed signal methodology | mixed signal solution | Open Access | STA | Verilog-AMS | timing model | FTM | Mixed-Signal | MCUs | encounter | Mixed-Signal Technology Summit | analog behavoral | analog behavioral models | analog/mixed-signal | mixed signal physical implementation open access | model validation | signal integrity | Virtuoso | Spectre | Cortex-M0 | oa | RNM | mixed signal methodology guide | real number types | Mixed signal physical implementation | behavioral models | mixed signal | OA: OpenAccess | cortex M | mixed-signal design | wreal | real number models | ARM | ARM-Cortex-M | OpenAccess | SPICE | mixed signal implementation | liberty model | simulation | AMS Verification
  • QiWang
    Mixed-Signal Technology Summit in Japan Provides Technology Updates
    By QiWang | 29 Nov 2012
    Japan’s semiconductor industry is undergoing a significant change in recent years. We are seeing a shrinking business in SoC development while design and semiconductor companies are trying to focus more on higher profitable and differentiable products like microcontrollers and power management ICs. Most such designs are mixed-signal designs and hence the demand for technologies and innovations in this area is very high...
    1 Comments
    Tags:
    AMS | uvm | Virtuoso-AMS | microcontrollers | ARM Cortex M0 | mixed signal design | Mixed-Signal On Top | AMS-Designer | MS ToT | IC 6.1 | A/MS | mixed signal methodology | tech on tour | AMS Designer | analog on top | Open Access | Cortex-M | Verilog-AMS | analog | Mixed-Signal | encounter | Mixed-Signal Technology Summit | LDE | analog behavioral models | analog/mixed-signal | Virtuoso | mixed-signal book | Cortex-M0 | oa | ClioSoft | metric-driven verification | mixed signal | wreal | micro-controllers | ARM | ARM-Cortex-M | OpenAccess | Common Power Format | AMS Verification | TowerJazz | Matlab | real number
  • AndreasLenz
    Discussing Mixed Signal -- New On-Line Forum, and 3-Day Training Classes
    By AndreasLenz | 15 Nov 2012
    Are you working in the area of mixed signal? Then you may want to exchange information and experiences with other engineers. At the Cadence Community, a new Mixed-Signal Design Forum has been launched, providing a place to discuss topics that cross between analog and digital domains. It doesn't matter if you're just starting with mixed-signal design, or you have a lot of experience. This is a customer-driven forum that...
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    Tags:
    ITDB | mixed-signal training | Andreas Lenz | analog on top | CPF | Mixed-Signal | encounter | Virtuoso | mixed signal | mixed-signal forum | OpenAccess | forum | Cadence Community
  • Sathish Bala
    Cadence Has Significant Presence in ARM TechCon 2012 and Worldwide ARM Technical Symposiums
    By Sathish Bala | 14 Nov 2012
    The recently concluded ARM TechCon 2012 , the annual event for ARM users (including hardware and software engineers) along with ARM ecosystem partners, was a huge success. Once again, this event showcased the excellent Cadence-ARM partnership that's helping to bring next generation electronic designs to fruition for our customers. Cadence had a huge presence at ARM TechCon. On the first day (Chip Design Day) Cadence...
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    ARM Techcon | EDI | chipestimate | ARM Cortex M0 | AMS Designer | ARM Technology Symposium | 20nm | 14nm | Mixed-Signal | Virtuoso | mixed-signal book | Cortex-M0 | mixed signal | mixed-signal design | ARM | ARM-Cortex-M
  • QiWang
    Recent Events Show That Customer Interest in Mixed-Signal Remains High
    By QiWang | 30 Oct 2012
    The well attended Mixed-Signal Technology Summit last month really demonstrated the tremendous interest our customers have in learning new methodologies and techniques for mixed-signal designs. I would like to share some interesting data points based on a survey from the attendees of the event. Among the close to 200 attendees, 73% were designers with analog centric design experiences. However, about 24% of them declared...
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    Tags:
    ARM Techcon | ARM Cortex M0 | mixed signal design | Technology on tour | MS ToT | mixed-signal ToT | mixed-signal methodology | mixed signal methodology | tech on tour | mixed signal solution | Open Access | Cortex-M | Mixed-Signal | Mixed-Signal Technology Summit | analog/mixed-signal | mixed-signal book | Cortex-M0 | Mixed-Signal Tech Summit | mixed signal methodology guide | mixed signal | OA: OpenAccess | cortex M | mixed-signal design | ARM | Mixed-Signal Methodology Book | tech-on-tour | OpenAccess | AMS Verification
  • Sathish Bala
    Press Release About TSMC Flow, Blog from ARM Validate Cadence’s Mixed-Signal and 20nm Leadership
    By Sathish Bala | 19 Oct 2012
    A press release and a blog post caught my attention this week (October 15, 2012), and they have clearly demonstrated Cadence's leadership in 20nm process nodes and mixed-signal solutions. The press release is titled " TSMC Selects Cadence Virtuoso and Encounter Platforms for its 20nm Design Infrastructure, Spanning Custom/Analog, Digital and Mixed-Signal Design ." This press release emphasizes that TSMC's 20nm reference...
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    Tags:
    AMS | EDI | ets | uvm | microcontrollers | ARM Cortex M0 | Mixed-Signal On Top | MS ToT | cadence | AMS Designer | TSMC | EPS | Mixed-Signal | Virtuoso | mixed signal methodology guide | mixed signal | PVS | ARM | encounter power system | Encounter Timing System | IUS
  • Sathish Bala
    ARM-Based Microcontrollers using Cadence’s Mixed-Signal Solution
    By Sathish Bala | 25 Sep 2012
    I recently came across a Wall Street Journal article, "ARM Chases Bigger Slice of Smaller Chips," that provides a very interesting perspective on how ARM is positioned to capture the microcontroller market, which is its next growth area. ARM based microprocessors are clearly dominating the mobile products from smart phones to tablets across Windows, Android and IOS mobile eco-systems. Most of these devices are using...
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    Tags:
    DAC | microcontrollers | Demo | Cortex-M | MCUs | Virtuoso | Cortex-M0 | incyte | fuel injection system | System Design Kit | micro-controllers | ARM | Balasubramanian
  • Sathish Bala
    Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM
    By Sathish Bala | 27 Aug 2012
    Even though it's been over 2 months since this year's Design Automation Conference in San Francisco, I am still surprised by the response that metric-driven, mixed-signal verification gets from our design community. Cadence had quite a few customer presentations at the EDA360 Theater at DAC this year. However, there was one presentation titled "Metric Driven Verification Approach for Analog/Mixed Signal IPs" authored...
    0 Comments
    Tags:
    real number modeling | DAC | uvm | IP | A/MS | Verilog-AMS | analog | co-simulation | Mixed-Signal | analog behavioral models | analog/mixed-signal | model validation | RNM | metric-driven verification | VHDL-AMS | assertions | mixed signal | mixed-signal design | wreal | real number models | Design Automation Conference | SPICE | mixed-signal verification | verification | stmicroelectronics | real number
  • QiWang
    Mixed-Signal Gets Clear Message in China
    By QiWang | 10 Jul 2012
    While most of my colleagues in the US were taking a nice break during the July 4 th week, a small group of people including me was on the road for a mixed-signal Tech-on-Tour in China. There was some debate internally on whether designers in China would be interested in such a topic. What we had experienced last week was a clear (not mixed) signal from the IC designer community in China that they are hungry for knowledge...
    0 Comments
    Tags:
    mixed-signal seminars | Beijing | AMS | China | mixed signal design | Technology on tour | mixed-signal ToT | mixed-signal methodology | mixed signal methodology | tech on tour | mixed signal solution | analog | Mixed-Signal | Shenzhen | mixed signal methodology guide | mixed signal | ARM | tech-on-tour | Shanghai | AMS Verification | mixed-signal verification
  • QiWang
    Tech-On-Tour: Bringing Advanced Mixed-Signal Design Methodology from Concepts to Reality
    By QiWang | 19 Jun 2012
    About a year ago, Cadence offered a worldwide Tech-On-Tour (ToT) series for mixed-signal designs. One main objective of this seminar series is to bring the awareness of the need for a design methodology change to the broad mixed-signal designer community worldwide. The event was very successful and you can find some previous blog coverage here: M/S Technology on Tour Blog - Model Validation and Assertion Based Verification...
    1 Comments
    Tags:
    DAC | Technology on tour | mixed-signal methodology | tech on tour | CPF | Mixed-Signal | encounter | Virtuoso | Cortex-M0 | incyte | mixed signal | Mixed-Signal Methodology Book | tech-on-tour | OpenAccess
  • QiWang
    What’s Hot for Mixed-Signal At DAC?
    By QiWang | 31 May 2012
    Analog/mixed-signal design is a hot topic at the Design Automation Conference! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), you can keep up with the latest developments in mixed-signal design methodology, including design, implementation and verification. You will find it is very hard to choose from so many options. Here is a quick guide to presentations, demos and other events Cadence is involved...
    0 Comments
    Tags:
    DAC | AMS | mixed signal design | mixed-signal methodology | mixed signal methodology | mixed signal solution | 28nm | 20nm | Advanced Node | Low-Power | Mixed-Signal | mixed signal physical implementation open access | mixed-signal book | mixed signal methodology guide | low-power design | mixed signal | cortex M | mixed-signal design | power | Design Automation Conference | mixed signal implementation | digitally assisted analog | mixed-signal verification
  • QiWang
    Cadence To Release the Industry's First Mixed-Signal Methodology Book
    By QiWang | 26 May 2012
    The new era of “Internet Everywhere” creates a whole new spectrum of applications, ranging from health care, automotive, to entertainment and cloud computing, which demand more and more mixed-signal and low power designs. In fact, mixed-signal applications have become one of the fastest growing segments in the electronics and semiconductor industry. Traditional mixed-signal designs treat the analog and digital designs...
    0 Comments
    Tags:
    AMS | mixed signal design | mixed-signal methodology | mixed signal methodology | mixed signal solution | analog | Mixed-Signal | mixed-signal book | dac2012 | mixed signal methodology guide | Mixed signal physical implementation | DAC 2012 | mixed-signal design | mixed signal implementation | mixed-signal verification
  • AndreasLenz
    Managing Inherited Connections with CPF in Virtuoso
    By AndreasLenz | 23 May 2012
    Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist needs to be imported into Virtuoso. Why use CPF? The Common Power Format (CPF) describes the design power intent for the whole...
    0 Comments
    Tags:
    inherited connections | EDI | Low Power | mixed signal solution | CPF | analog | Mixed-Signal | encounter | Verilog | mixed signal physical implementation open access | Virtuoso | oa | Mixed signal physical implementation | mixed signal | OA: OpenAccess | mixed-signal design | Virtuoso environment | mixed signal implementation | design implementation | Common Power Format
  • paragb
    A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs
    By paragb | 16 May 2012
    The purpose for creating a Pcell is to automate the creation of data. Pcells should be designed as standalone entities, independent of the environment in which they are created and independent of the variety of environments in which you or someone else might want to use them. An environment can react to a Pcell, but Pcell code should not react to, interact with, or be dependent on an environment. Although it is possible...
    0 Comments
    Tags:
    ECO | Static timing analysis | EDI | mixed signal design | parasitic | IC 6.1 | mixed signal solution | Open Access | STA | timing model | ECOs | mixed-signal ECOs | Mixed-Signal | encounter | Virtuoso | oa | EDIS | ECOs and PCells | Mixed signal physical implementation | mixed signal | signoff | OpenAccess | Virtuoso environment | mixed signal implementation
  • QiWang
    What is Digitally Assisted Analog Design?
    By QiWang | 30 Apr 2012
    Mixed-signal applications are among the fastest growing segments in the electronics and semiconductor industry. Applications in mobile communication, networking, power management, automotive, medical, imaging, safety and security require a very high integration of analog and digital functionality at system, SoC and IP levels. Unfortunately, compared with the advancement of digital designs over the past decade, the state...
    0 Comments
    Tags:
    daa | AMS | Low Power | mixed signal design | mixed signal solution | Mixed-Signal | dac2012 | Mixed signal physical implementation | mixed signal | cortex M | DAC 2012 | ARM | boris murmann | digitally assisted analog | mixed-signal verification
  • AElzeftawi
    CDNLive! -- Real Number Model Development and Application in Mixed-Signal SoC Verification
    By AElzeftawi | 9 Apr 2012
    With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital content in response to new functionality demands, and steady growth of IP blocks into larger and larger SoCs, traditional AMS verification flows are becoming inefficient in handling full chip verification. High-performance digital verification and high accuracy analog verification represented the foundation for traditional AMS verification...
    0 Comments
    Tags:
    real number modeling | CDN Live | CDNLive SV 2012 | CDNLive | AMS Designer | LSI | RNM | behavioral models | CDNLive! | wreal | Luo | Virtuoso environment | AMS Verification | mixed-signal verification | verification
  • PrabalB
    DVCon 2012: Bringing Continuous Domain into SystemVerilog Covergroups
    By PrabalB | 30 Mar 2012
    On the last day of February 2012, I presented a proposal at the DVCon 2012 Conference to extend SystemVerilog to support a real data type in coverpoint objects in order to facilitate mixed-signal verification for functional coverage. The paper, titled “ Bringing Continuous Domain into SystemVerilog Covergroups, ” reflected a year-long effort between Cadence R&D and Scott Little of Freescale (Scott moved to Intel just...
    0 Comments
    Tags:
    SystemVerilog | coverage | covergroups | Functional Verification | analog | Mixed-Signal | DVcon | real number types | functional coverage | mixed signal | floating point | mixed-signal verification | verification | real number
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