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IC Packagers: Mysteries Revealed - Why is Flip-Chip Chip-Down the Default Library Die Orientation?

By Tyler | 28 Jan 2020

We’ve come to the end of my New Year’s Resolutions for 2020. Before we dive deeper into the exciting new capabilities to be found in the 17.4 release, though, I’d like to address a question I hear from new users all the time. That q...

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Allegro Package Designer
IC Packagers: Symbol Editing in IC Packages - Choose the Right Option

By Tyler | 21 Jan 2020

When you need to make an edit to a component, whether that is the BGA footprint in need of a pin #1 padstack change for reference of adjustments to the entire bump layout of a flip-chip to feed routability changes back to the IC design team, there ar...

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Allegro Package Designer
IC Packagers: The Default Bond Wire Profile - PROFILE1 (And Three Reasons Why Not to Use It)

By Tyler | 14 Jan 2020

For those of you who do wire-bond package substrate – whether you’re designing a single-chip leadframe, a multi-die memory stack, or a complex stack with wire-bonds, flip-chips, interposers, and spacers all in one – you need wire pr...

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Allegro Package Designer
IC Packagers: Four Reasons to Avoid Multi-Layer Flip-Chip Pin Padstacks

By Tyler | 7 Jan 2020

Designing a package substrate, there are things that many of us do that perhaps we should think twice about. One of those being using a multi-layer padstack for the pins of flip-chip dies. I understand the attractiveness of doing this, but if you’ll give me just a few moments, perhaps I can convince you to put ...

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Allegro Package Designer
IC Packagers: Stepping into 2020

By mrigashira | 30 Dec 2019

We started 2019 with the promise to cover all the topics that might interest you as we go, looking at a new area every week. To keep this promise we had a whole lot of exciting tasks. To start with we needed to know what you want to re...

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Allegro Package Designer
IC Packagers: Routing Clean-Up Prior to Manufacturing

By Tyler | 29 Dec 2019

A fantastic year is ending, so I want to take a quick opportunity to go over some of the lesser-known commands available to you for cleaning up and optimizing your routing for manufact...

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Allegro Package Designer
IC Packagers: Guiding Your Team with Workflows

By Tyler | 24 Dec 2019

The flow for efficiently and correctly designing a package substrate layout is a complex task. Many teams define steps to be followed by designers to make sure that rul...

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APD
IC Packagers: An Introduction to Allegro Package Designer Plus in 17.4

By Tyler | 17 Dec 2019

Some of you are APD users, building single-chip or non-stacked multi-chip packages. Others of you are SiP Layout XL users, probably stacking dies or embedding elemen...

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17.4 | APD | SiP Layout
IC Packagers: Copy and Paste Refresh in 17.4

By Tyler | 10 Dec 2019

The most common operations in any tool are probably adding, moving, deleting… plus copying and pasting. That we all are familiar with Control-C and Control-V being shortcuts to these actions speaks to their applicability across tools we use ev...

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allegro 17.4 | APD | Allegro Package Designer | Allegro
IC Packagers: The Third Dimension of 17.4 IC Packaging

By Tyler | 3 Dec 2019

If you’ve run the 17.4 release, you have probably seen two 3D rendering tools – 3D Viewer and 3D Canvas – present in the View menu. Why are there two? That’s a good question, and the answer lies in the type of design you ...

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17.4 | APD | 3d model
IC Packagers: Materially Good Changes in 17.4

By Tyler | 26 Nov 2019

You should be getting used to the new 17.4 release at this point. I am willing to bet there are still exciting new improvements that you haven’t found yet. Today, allow me to show off the new materials editor. It is likely you don’t...

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17.4 | APD
IC Packagers: A Cross-Section of Changes

By Tyler | 19 Nov 2019

While 17.4 has only been amongst you for a month, now, I’ve had a few questions regarding manipulating your layer stack-up in the new release. We covered scripting changes previously, but a quick chat about the general use model is warranted. T...

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APD
IC Packagers: Plan Your Escape with Modernized Structures

By Tyler | 12 Nov 2019

Many of you, our regular readers, are familiar with via structures. These reusable patterns of vias, clines, shape, and keep-out shapes, and return path elements allow you to escape a single pin then replicate that structure (or pattern of structures...

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17.4 | APD
IC Packagers: Scripting Updates in 17.4

By Tyler | 6 Nov 2019

If you joined us last week to see the visual changes to be expected when you download 17.4, doubtless the next thing you need to know is how migrating will impact your automation. And, if you’ve installed the software already, you’re one ...

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APD | PCB Editor
IC Packagers: Welcome to 17.4!

By Tyler | 30 Oct 2019

It’s here! Less than two weeks ago, on October 18, 2019, Cadence released the 17.4-2019 version of the Allegro product line. This means exciting new features, enhancements, bug fixes, and performance improvements to the tools you depend on to d...

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17.4 | APD
IC Packagers: Manage Your Outside Data Sources in One Place

By Tyler | 22 Oct 2019

Every package design has data sources. Die data you receive from the IC design team as they send you updated die text files and co-design die abstracts. Your downstream PCB design team may send an updated ball map spreadsheet with change requests. Obviously, your front-end schematic engineer will be pushing you updated netlist information. How do you keep track of when the last time was that you imported data from a...

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APD | PCB Editor | SiP Layout
IC Packagers: Optimize Display Settings for Faster Screen Redraws

By Tyler | 15 Oct 2019

While designing interposers and very high pin count device packages, as the number of objects to manipulate increases, you may notice that the display takes longer to draw. This is for a very good reason: by default, the tools will draw everything.....

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PCB | APD | SiP Layout
IC Packagers: Undoing Your Custom SKILL Commands

By Tyler | 8 Oct 2019

Today, we’ll talk about something simple but still important. For all of you who write your own SKILL code commands to help your teams be more productive, this one’s for you. Any time you are modifying the database, it is important that y...

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APD | SiP Layout | SKILL
IC Packagers: Wrap Your Hands Around a Coil

By Tyler | 1 Oct 2019

Coils are a design element that, if not exceedingly common, are showing up in more designs these days. They appear simple at first glance, but keeping a consistent air gap between each revolution of the spiral can involve a lot of mental arithmetic and picks in the design canvas. Here's how to do this with a few short clicks?

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SiP Layout
IC Packagers: Finding Design Issues in SiP - Three Options for DRC Management During Sign Off

By Tyler | 24 Sep 2019

Your design is complete. Yet, you have 20 DRC violations that need to be addressed (whether that means correcting the constraint required value, modifying objects, or waiving the DRC to sign off on it as okay). What’s the best way to go about r...

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APD | SiP Layout
IC Packagers: Capture Your Design for Review

By Tyler | 17 Sep 2019

How do you quickly show another developer an issue that concerns you? Do you need to send them the entire design, start a screen sharing session, or bring up the Symphony server and allow them to connect? All of these are GREAT review mechanisms; however, they aren’t always viable or convenient.

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APD | SiP Layout
IC Packagers: How Far Away are You?

By Tyler | 10 Sep 2019

Layout design is all about clearances. Daily challenges come from maintaining consistent space between your differential pair members, calculating the number of routing channels you can squeeze between two vias, or ensuring adequate clearance of bond...

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SiP Layout
IC Packagers: Manufacturing Cross-Hatched Shapes

By Tyler | 3 Sep 2019

If you use cross-hatched shapes in your package design, you are doubtless aware of some considerations. Namely, if your shape outline is anything but a rectangular outline at a multiple of the hatch line width pattern, and unless it has no objects to...

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SiP Layout
IC Packagers: Rule Your Package Designs

By Tyler | 27 Aug 2019

When it comes to package design, spacing often reigns supreme. The location readout in the bottom status bar of the tool will always tell you where your cursor is in the design; this can show either absolute or relative mode (in which case coordinate...

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SiP Layout
IC Packagers: Choosing the Right Netlist to Match Your Needs

By Tyler | 20 Aug 2019

Netlists. Everyone needs them! But what you are using your netlist for can have a significant influence on just what KIND of netlist you want. Fortunately, the Cadence SiP tools offer formats for just about every situation you might run into, from in...

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APD | IC Packaging & SiP design | SiP Layout

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