IC Packaging and SiP Blogs

The HotFix 028 of our 17.4-2019 release was rolled out at the end of March and is now available for download and installation. The release brings critical bug fixes, product enhancements, and new features. Let’s talk about some of the exciting...

Hello, everyone, and a happy new year! Last year was incredibly exciting for IC Packaging, with all the emerging options coming with silicon interposers, 3DIC innovations, and so much more. The options we are seeing continue to expand at lightning sp...

So, here we are, saying a big thank you, and presenting a list of some of the most popular posts of 2021 in the ...

The demand for smaller electronics devices can be achieved by high-density layers in multi-layer build-up substrates or multi-layered printed circuit boards (PCB). Vias are essential in the design and manufacturing process of multi-layered packages ...

It is quite common to reuse memory stacks across designs. These memory stacks are created as modules (.mdd) and saved in a library, which can then be used in different package designs. You can place a memory stack module depending on the capacity of ...

In Allegro® Package Designer Plus prior to the HotFix 019 of release 17.4-2019, any component of type IC in the design shows up in Die-stack Editor. If these are off-the-shelf components, you do not want to see them in Die-stack Editor. To stop s...

This marks our third and final look at the biggest new features in this major update. We’ve already looked at features spanning from performance gains to improvements in the graphical canvas. Updates to the base product and items for the advanc...

Last week we looked at new features largely targeting your manufacturing flow. Layer-based degassing improvements, acute angle corrections, and tools to perform a layout-vs-layout comparison of your intended manufacturing mask against the original de...

The HotFix 019 of our 17.4-2019 release is available for download and installation, now. This marks our third major update of this release stream, and that means a host of bug fixes, enhancements, and new features. I’m excited to get to ta...

Most package designs have wire bonding and reusing the wire bond information for other similar dies placed in the design significantly improves the efficiency and reduces the turnaround time. Allegro Package Designer Plus provides Place replicat...

Design complexity and space constraints are pushing designers to innovative novel solutions. Placing a die inside a cavity is the most common and effective technique and you have most probably used it if you are designing an application for the auto...

Design reuse is the key to faster design cycles in today’s packaging design industry, where the shortest possible time to market makes or breaks the success of a product. As most of the package designs have wire bonding, sharing the wire bondin...

In today's ever-shrinking IC Package design cycles, it is almost imperative that we catch and correct routing issues as early as possible, which makes simulation an integral part of the design cycle. Layout engineers want a quick and accurate way to ...

The task of IC/package co-design causes multiple challenges during the design cycle and one of them is to update the netlist of co-design die or BGA in the middle of the design cycle. The current process of updating connectivity provides no flexibili...

Let’s focus today on an established routing technology with a new twist! All of you are doubtless familiar with the concept of structures – formerly called via structures, renamed to structures because of their growing flexibility and application across many flows.

All of you doing advanced node package or silicon interposer substrate design in Allegro® Package Designer know what degassing is. And, while we talked last summer about massive performance improvements (plus additional information in show elemen...

I could doubtless extend this series all year long, covering the important updates, improvements, and completely new functionality that is continually being added to the Allegro® Package Designer product. This will be my last before we shift back...

As promised, we’re back with some more of the big improvements that are part of the QIR2 update release of 17.4 (HotFix 013). This time, everything is specific to our Allegro® Package Designer Plus community. Without further ado, then, let&...

Welcome to a brand-new year, everyone! As we welcome in 2021, we also welcome the next major update to the 17.4 Allegro platform release in the form of QIR2 (hotfix 13). These new updates are exciting for many reasons. Of course, they bring bug fixes...

And so, here we are at the end of the year. I do hope that our weekly IC posts livened up 2020's groundhog days full of online meetings, washing up, and frantic searches for an Icelandic crime series you haven't yet watched! As we take stock ...

Some items are useless on multiple levels. The most common multi-class pairing is probably the package substrate outline and the route/component keep-in shapes. Since it’s unwise to route or place anything off the edge of the world, it is impor...

ECOs. Without them, the lives of designers would be so much easier! Imagine a world where the original requirements you were given never changed throughout the design. Unfortunately, such a world, as we know, does not exist. How, then, can you track ...

Are you like me? Do you forget things and have a running to-do list for your designs? Would you like to leave instructions and comments for your colleagues to remind them of actions needing doing? There are many places to record this type of informat...

More package designers these days, with the increasing component counts and more complicated electrical constraints, are shifting to using a front-end schematic capture tool. As with IC and PCB design, this allows for verification between the logical...

Back at the start of 2020, we talked about why you shouldn't use the default wire profile in your actual design. Today, I want to take this a step further. If you do wire bond designs, you are doubtless aware of the certified bond wire profiles t...