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We have all heard about co-design, how it is going to get us to market on time, reduce our layer counts, and give us the ability to trade off design decisions at different layers of the system substrates. If you're reading this blog, you almost certainly know about the co-design capabilities present in the Cadence SiP Layout tools—features that allow you to "see into" the IC substrate to the driver cell positions and make intelligent tradeoffs.
Did you know, though, that you can also export a view of the package substrate and overlay it on your IC design canvas in the Cadence digital design tools to get that same context on the other side of the fence? If you didn't, and you're interested in all the power this ability can give you, keep reading to learn more about this exciting ability!
To see the package routing and other context information inside your IC tool, you need to have the 16.6 release of the Cadence SiP Layout XL tool and a co-design die in your substrate design. This can be either a distributed co-design die, managed through a die abstract, or a concurrent co-design die using Open Access (Note: additional licensing options required for the concurrent flow).
By running the File -> Export -> Package Overlay File for IC command, you are presented with a form that looks like the following:
Once you've picked the placed die instance in your package (that name in brackets is your IC design name, by the way), simply enter a file name and tell the tool everything you want exported to be visibly available in your IC design window.
Not only can you pick multiple substrate layers, but you can also restrict the region (maybe you only care about the escape routing under the die itself) and the substrate object types (do you only need to see the bond shell and the cavity boundary around your wire bonded die?). The exported file is intelligent, too! Because this is written for a co-design die, the SiP Layout tool has all the information it needs to include both the IC net AND the package net. Best of all, though, the view is rotated back for proper orientation when overlaid on the IC design. It's even scaled automatically into your IC design units, taking any die shrink into account!
Now that you've generated a view of your package substrate, what do you do with it? If you're an Encounter user, it is time to open your IC layout for this chip and overlay this new contextual information on top of it to give you even more awareness and exposure to how changes you make to the top-level routing and I/O cell and bump positions will impact the package substrate.
From the Encounter command line, run the command "readPackage <filename>". Note that you need to be in the Floorplan View in order to see the package substrate display, though. Curious what you can expect? Take a look at this example:
You can see the BGA balls around the outside, complete with ratsnest/flight lines from the die bumps out to their corresponding balls. Encounter even gives you the ability to control the color and visibility of the various package object types, as you can see here:
This is all well and good if you are a First Encounter user. But, what if you use Virtuoso, you ask? Or, for that matter, what if you just want to use this in your own internal tool to compare all the different package substrates that your chip may be used in?
Have no fear! Because this is a plain text XML file with a simple format, you are free to write your own parsers to read and generate displays of this data in the tool of your choice. You don't need to worry about trying to parse many different XML structures for all the different object classifications, either. Bond fingers, routing traces, plane shapes with degassing arrays... all objects are polygon outlines with an object type and name. In this way, if the SiP tool adds new routing object types in the future, your parser will automatically support them.
Now that you know about this file, its contents, and some of its uses, are you inspired with an idea of how to use it in another way? Or have you thought of a different enhancement to the IC Packaging tools that will make your design flow simpler, faster, or more consistent? If so, we would love to hear all of your ideas. We'll make sure they get heard by the rest of the package design community and the Cadence IC Packaging engineering team!