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The following question has come up in
comments: "How do I measure Fmax for an MOS transistor?" The
measurement methodology -- testbench, analysis, calculator setup, stimulus, etc.--
does not change whether you are measuring bipolar transistors or MOS
transistors. On the other hand, the results for MOS transistors often come out
looking wrong, or more correctly, non-physical.
Before scratching your head,
adjusting your testbench or doing anything else, you need to consider the model
that you are using. For review the fmax testbench is shown below. The testbench
has two control loops -- a dc control loop that controls the drain current, and an
ac loop that for measuring the s-parameters of the transistor. The control
loops are isolated using inductors (dc short, ac open) and capacitors (dc open,
ac short). You could use
analysis-dependent switches in place of the inductors and capacitors if you prefer.
Figure 1: Fmax Testbench
Using this testbench, let's explore some different approaches
to modeling a MOS transistor and see what happens. We will look at three
different device modeling approaches:
Using the standard bsim3v3 model
Using the standard bsim3v3 model with RF
extensions. The BSIM3v3 model does not account for the extrinsic elements of
the MOS transistor that can affect the RF performance of the transistor, for
example, the resistance of the gate, the substrate resistance, etc.
bsim4 model. The bsim4 model includes the extrinsic components within the
We won't discuss the details
of device modeling in this blog, if you are interested, you can find more
information in the reference. Please note that approach 2 and approach 3 are
equivalent methods of implementing the model extensions discussed in the
To compare the models, we
will start by simulating the maximum unilateral gain in order to find the Fmax, The results are shown in Figure 2 below. Let's look at what the simulation
results are telling us about the transistor models. The results for the default
bsim3v3 model look non-physical since the maximum unilateral gain has large
peaks in the response at frequencies above 10GHz and the response does not roll
off until almost 100GHz. However, both the bsim3v3 with RF extensions and the
bsim4 model show the results we would expect, the gain is flat at low
frequencies and rolls-off at high frequencies.
One additional comment about
the simulation results. Due to some PDK limitations, the bsim3v3 models are
from a 180nm feature size PDK, while the bsim4 data is from a 45nm feature size
PDK. So the simulated Fmax is
different due to process scaling and not due to differences in the modeling
approach. For devices from the same PDK modeled using the two approaches, the Fmax
should be consistent.
Figure 2: Comparing the Maximum
In previous blog posts, we have
discussed the good things that simulation allows you to do, that is, perform
measurements that you cannot perform in the real world. Idealizing testbench behavior
or, more correctly, including exactly the phenomena that the designer
specifies, is good when creating testbenches. The simulation will ignore
all the higher order phenomena that degrade measurement accuracy.
example, we can measure ft directly in simulation instead of
extracting it from s-parameters as we would have to do if we tried to measure
it in the lab. On the other hand, simulation also ignores all the higher order
device behavior that designers do not specify. As a result, effects that can
degrade design performance are ignored.
The solution is to improve model
fidelity, which will also increase model complexity and simulation time. So
designers need to make a trade-off between how accurately to model a
transistor's characteristics and their objectives when simulating. While an RF
designer may want to use RF models, not everybody needs them. For example, if
you are designing a Band-Gap Reference, then you probably don't need to use an
RF model; you are more interested in modeling the effect of process variation
on the circuit.
summary, simulating the Fmax of a MOS transistor is similar to
simulating the Fmax of a bipolar transistor. As we discussed, you
can use the testbench to perform sanity checks on your models to verify that
they are appropriate for your application or select the best component from the
PDK for your application. You can also use the testbench to optimize the
performance for your operating conditions, that is, trade-off gate length and
gate width to give the best Fmax or Noise Figure for the given bias
MOSFET Model User's Manual, Morshed et al., Chapter 9, High Speed/RF
thanks for sharing this.
I think there is a small detail in the test bench that can have decisive influence on the outputs: the drain (source) current control loop. For DC, it is absolutely fine and elegant, but it has no BW limitation (that I could see from the schematic). "IFEEDBACK" should have a BW limitation in order to not regulate out the (small signal) RF currents in the source that are produced by the (small signal) input test port.
I put a voltage source (for a certain Id) instead of the feedback loop, got of course the same drain DC current (same bias setup) and my fmax changed (in my case it shifted upward). I could not see any useful change from the "AC=1" setting in the current source.
I noticed this when I used your circuit for NFmin "characterization", and there the NFmin came out far too high with the setup as described in this blog.
In my opinion, it would work better to place a 2nd transistor of same type/w/l in the schematic and use that device for the DC biasing feedback loop, and bias the RF gate from that same point.
Looking fwd to discuss this with you.
Useful testbench to compare the different BSIM models
A good Figure of Merit to look at semiconductor process trade-offs if studying the fT and FMAX is to actually plot: fT x gm/Id as function of Vgs-Vt (overdrive) of selected processes. This will give you a plot and a good idea of optimizing the bias for the best performance in your design. This could be helpful when re-centering a migrated design.