Going broadside with electromagnetic modeling of advanced processes

9 Oct 2008 • 2 minute read

It has caught my attention that designs using fabrication processes such as 65nm, 45nm, 32nm, and smaller, have changed the landscape when it comes to electromagnetic (EM) modeling of components and interconnects. These designs have to contend with the pronounced effects of increased broadside coupling. This is a result of the change in aspect ratio in the metal where it is now taller than wider in these new processes.

The ability to mesh the sidewalls in planar EM solvers is key to addressing the challenges posed by these smaller process. Those challenges directly affect the accuracy of the modeling results. Having accurate characterization of the EM effects has a direct impact on the viability of the design and minimizes the risk of the design failing. Not being able to predict this is not good news when it comes to using those results in subsequent circuit simulations to predict performance and tolerance of the process variations.

Those effects of increased broadside coupling due to the change in aspect ratios (which exposes much more metal on the walls of the metal traces), creates more capacitive coupling between interconnects and in the various components fabricated within the die. This directly impacts component properties such as Q (quality factor), reactance, and a variety of conductive losses. Let’s not forget the dependence on frequency in these properties.

There is a second effect to consider and that is the series resistance of the conductor. At frequencies where the skin depth is on the same order as the width and height of the interconnect, the current crowds near the surface of the metal. Since the conductor has significant height relative to width, a great deal of that current is also on the sidewalls, therefore, without sidewall modeling you can not get an accurate approximation of the conductor resistance. This will have significant impact in calculation of the Q, especially peak Q, which occurs at frequencies where this phenomena plays a big role.

Virtuoso RF Designer provides those capabilities that can better model EM effects found in the advance process nodes at 65nm and smaller. RF Designer being tightly integrated within a Virtuoso design flow, makes it easy to model those structures and geometries for the designer or EM specialist. Furthermore, RF Designer does not require simplification of those structures for the solver to be able to complete its task.

Since you can’t get something for nothing, and sidewall modeling fits the case, it maybe worth mentioning that with other planar solvers utilizing 3D sidewall modeling, it can result in a big penalty on the time it takes the solver to complete its work. Thus far the impact of 3D sidewall modeling within RF Designer has not resulted in a significant increase in the amount of time it takes for the solver to finish. This is a result of the core technology within RF Designer which accelerates the solver. This is something worth considering when you think about EM modeling within your design flow.

These are just two of the RF related EM effects we are seeing in these smaller processes being used in high frequency RFIC design. I would like to see us have a conversation about this and other effects in this forum. What do you see as important effects for EM modeling to consider as the fabrication process continues to evolve? I’m curious.