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Inductors, transformers and transmission lines are critical components in any high frequency integrated circuit. Conventional electromagnetic tools used for the design of these components are difficult to setup, require electromagnetic expertise and are not integrated in IC design flows.
Traditionally, specialized modeling teams work hard for several months to design, fabricate and characterize a limited set of inductors and transformers for IC designers to choose from. They repeat this long and cumbersome procedure every time a new process node or a new design application is introduced, adding months to the overall design cycle. IC designers faced by a small selection of passive components and limited analysis capabilities are forced to over design wasting expensive Silicon area and increasing failure rates.
Virtuoso Passive Component Designer is a complete flow for the design, analysis and modeling of inductors, transformers and transmission lines. Tightly integrated with Virtuoso Schematic Editor and Virtuoso Layout Suite, the tool brings passive component design to the hands of analog and RF designers.
Starting from design specifications such as inductance, quality factor and frequency, designers can use Virtuoso PCD to automatically generate the optimum inductive device for their specific application and process technology, resulting in higher performance and smaller area. A built-in accurate 3D full wave solver is used to verify the generated devices, eliminating the need for a dedicated inductor characterization run and reducing the design turn-around-time.
Virtuoso PCD is easy to use and does not require electromagnetic expertise. The output is a complete PDK component with a symbol, schematic, layout and a simulation model. The built-in modeling capability converts S-parameter files into physical lumped element models, ready for RF analysis using Virtuoso Spectre Simulator XL and GXL. Virtuoso PCD also includes a fast and accurate coupling analysis capability enabling designers to optimize the placement of inductors and transformers on the layout resulting in smaller Silicon area and higher yield.
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